US12288497B2ActiveUtilityA1
Display panel, driving method thereof, and display device
Assignee: HUBEI YANGTZE IND INNOVATION CENTER OF ADVANCED DISPLAY CO LTDPriority: Jun 29, 2022Filed: Dec 1, 2023Granted: Apr 29, 2025
Est. expiryJun 29, 2042(~16 yrs left)· nominal 20-yr term from priority
Inventors:Jujian Fu
G09G 3/32G09G 2340/0435G09G 3/3233G09G 2360/16G09G 2320/0233G09G 2310/08G09G 2300/0861G09G 2300/0842G09G 2300/0819G09G 2320/0223G09G 2320/0238G09G 2310/0264G09G 3/20G09G 3/3225
78
PatentIndex Score
0
Cited by
21
References
20
Claims
Abstract
A pixel circuit in a display panel includes a drive transistor and a first transistor, a first terminal of the drive transistor is electrically connected to a power signal line, a first terminal of the first transistor is electrically connected to an initialization signal line; a second terminal of the first transistor is electrically connected to the drive transistor, or the second terminal of the first transistor is electrically connected to the light-emitting element; and drive modes of the display panel include a first drive mode, a second drive mode, and a third drive mode, the first drive mode corresponds to a first drive frequency F 1 and a first initialization signal V ref1 , the second drive mode corresponds to a second drive frequency F 2 and a second initialization signal V ref2 , and the third drive mode corresponds to a third drive frequency F 3 and a third initialization signal V ref3 .
Claims
exact text as granted — not AI-modifiedWhat is claimed is:
1. A display panel, comprising: a light-emitting element and a pixel circuit electrically connected to the light-emitting element, wherein
the pixel circuit comprises a drive transistor and a first transistor, wherein a first terminal of the drive transistor is electrically connected to a power signal line, a first terminal of the first transistor is electrically connected to an initialization signal line; wherein a second terminal of the first transistor is electrically connected to the drive transistor, or the second terminal of the first transistor is electrically connected to the light-emitting element; and
drive modes of the display panel comprise at least a first drive mode, a second drive mode, and a third drive mode, wherein the first drive mode corresponds to a first drive frequency F 1 and a first initialization signal V ref1 , the second drive mode corresponds to a second drive frequency F 2 and a second initialization signal V ref2 , and the third drive mode corresponds to a third drive frequency F 3 and a third initialization signal V ref3 , wherein F 1 >F 2 >F 3 , V ref1 ≠V ref2 , V ref1 V ref3 ,
F
2
-
F
3
F
1
-
F
3
≠
❘
"\[LeftBracketingBar]"
V
ref
2
-
V
ref
3
❘
"\[RightBracketingBar]"
❘
"\[LeftBracketingBar]"
V
ref
1
-
V
ref
3
❘
"\[RightBracketingBar]"
.
2. The display panel according to claim 1 , wherein
F
2
-
F
3
F
1
-
F
3
<
❘
"\[LeftBracketingBar]"
V
ref
2
-
V
ref
3
❘
"\[RightBracketingBar]"
❘
"\[LeftBracketingBar]"
V
ref
1
-
V
ref
3
❘
"\[RightBracketingBar]"
.
3. The display panel according to claim 1 , wherein |V ref2 −V ref3 |>|V ref1 −V ref2 |.
4. The display panel according to claim 1 , wherein the drive modes of the display panel comprise an i-th drive mode and a j-th drive mode, and the j-th drive mode comprises a signal writing stage and a light emission holding stage, wherein i and j are both integers, and i≠j; and
the i-th drive mode corresponds to an i-th drive frequency F 1 and an i-th initialization signal V ref1 , the j-th drive mode corresponds to a j-th drive frequency F 1 , the signal writing stage in the j-th drive mode corresponds to a j1-th initialization signal V refj1 , and the light emission holding stage in the j-th drive mode corresponds to a j2-th initialization signal V refj2 ;
wherein F j <F 1 , and |V ref j2 |>|V ref j1 |>|V refi |.
5. The display panel according to claim 1 , wherein the drive transistor comprises a P-type transistor, and V ref3 <V ref2 <V ref1 <0; or
the drive transistor comprises an N-type transistor, and V ref3 >V ref2 >V ref1 >0.
6. The display panel according to claim 1 , wherein the drive modes of the display panel comprise a k-th drive mode and an 1-th drive mode, and the k-th drive mode is a dominant-frequency drive mode; and
the k-th drive mode corresponds to a k-th drive frequency F k and a k-th initialization signal V refk , and the 1-th drive mode corresponds to an 1-th drive frequency F 1 and an 1-th initialization signal V ref1 ;
wherein F 1 <F k , and F k is an integer multiple of F 1 , and
❘
"\[LeftBracketingBar]"
V
refk
-
V
ref
1
❘
"\[RightBracketingBar]"
=
(
F
k
F
l
-
1
)
×
0.1
.
7. The display panel according to claim 1 , wherein the drive modes of the display panel comprise an s-th drive mode and a w-th drive mode, and the w-th drive mode is a highest-frequency drive mode; and
the s-th drive mode corresponds to an s-th drive frequency F s and an s-th initialization signal V ref s , and the w-th drive mode corresponds to a w-th drive frequency F w and a w-th initialization signal V ref w ;
wherein
F
w
-
F
s
F
s
×
30
≤
❘
"\[LeftBracketingBar]"
V
refs
-
V
refw
❘
"\[RightBracketingBar]"
≤
F
w
-
F
s
F
s
×
10
.
8. The display panel according to claim 1 , wherein
the first drive mode further corresponds to a first power signal V dd1 , the second drive mode further corresponds to a second power signal V dd2 , and the third drive mode further corresponds to a third power signal V dd3 ;
wherein
F
2
-
F
3
F
1
-
F
3
≠
❘
"\[LeftBracketingBar]"
V
dd
2
-
V
dd
3
❘
"\[RightBracketingBar]"
❘
"\[LeftBracketingBar]"
V
dd
1
-
V
dd
3
❘
"\[RightBracketingBar]"
.
9. The display panel according to claim 8 , wherein
F
2
-
F
3
F
1
-
F
3
<
❘
"\[LeftBracketingBar]"
V
dd
2
-
V
dd
3
❘
"\[RightBracketingBar]"
❘
"\[LeftBracketingBar]"
V
dd
1
-
V
dd
3
❘
"\[RightBracketingBar]"
.
10. The display panel according to claim 8 , wherein |V dd2 −V dd3 |>|V dd1 −V dd2 |.
11. The display panel according to claim 8 , wherein the drive modes of the display panel comprise an m-th drive mode and an n-th drive mode, and the n-th drive mode comprises a signal writing stage and a light emission holding stage, wherein m and n are both integers, and m≠n;
the m-th drive mode corresponds to an m-th drive frequency F m and an m-th power signal V ddm , the n-th drive mode corresponds to an n-th drive frequency F n , the signal writing stage in the n-th drive mode corresponds to an n1-th initialization signal V ddn1 , and the light emission holding stage in the n-th drive mode corresponds to an n2-th initialization signal V ddn2 ;
F n <F m ; and
the drive transistor comprises a P-type transistor, and V dn2 >V dn1 >V ddm >0; or the drive transistor comprises an N-type transistor, and 0<V ddn2 <V ddn1 <V ddm .
12. The display panel according to claim 8 , wherein the drive transistor comprises a P-type transistor, and V dd3 >V dd2 >V dd1 >0; or
the drive transistor comprises an N-type transistor, and 0<V dd3 <V dd2 <V dd1 .
13. The display panel according to claim 8 , wherein
❘
"\[LeftBracketingBar]"
V
ref
2
-
V
ref
3
❘
"\[RightBracketingBar]"
❘
"\[LeftBracketingBar]"
V
ref
1
-
V
ref
3
❘
"\[RightBracketingBar]"
>
❘
"\[LeftBracketingBar]"
V
dd
2
-
V
dd
3
❘
"\[RightBracketingBar]"
❘
"\[LeftBracketingBar]"
V
dd
1
-
V
dd
3
❘
"\[RightBracketingBar]"
.
14. The display panel according to claim 8 , wherein |V dd1 −|V ref1 |>|V dd2 −|V ref2 |>|V dd3 −|V ref3 |.
15. The display panel according to claim 8 , wherein the drive modes of the display panel comprise a p-th drive mode and a q-th drive mode, and the q-th drive mode is a dominant-frequency drive mode, wherein p and q are both integers, and p≠q;
the p-th drive mode corresponds to a p-th drive frequency F p , a p-th initialization signal V refp , and a p-th power signal V ddp , and the q-th drive mode corresponds to a q-th drive frequency F q , a q-th initialization signal V ref q , and a q-th power signal V ddq ; and
the drive transistor comprises a P-type transistor, and
(
V
ddp
-
V
refp
)
=
(
V
ddq
-
V
refq
)
+
(
F
q
F
p
-
1
)
×
0.1
;
or
the drive transistor comprises an N-type transistor, and
(
V
refp
-
V
ddp
)
=
(
V
refq
-
V
ddq
)
+
(
F
q
F
p
-
1
)
×
0.1
;
wherein F q is an integer multiple of F p .
16. The display panel according to claim 1 , wherein the second terminal of the first transistor is electrically connected to a gate of the drive transistor; or the second terminal of the first transistor is electrically connected to a second terminal of the drive transistor through a second transistor.
17. A driving method of a display panel, which is applied for driving a display panel, wherein the display panel comprises
a light-emitting element and a pixel circuit electrically connected to the light-emitting element, wherein
the pixel circuit comprises a drive transistor and a first transistor, wherein a first terminal of the drive transistor is electrically connected to a power signal line, a first terminal of the first transistor is electrically connected to an initialization signal line; wherein a second terminal of the first transistor is electrically connected to the drive transistor, or the second terminal of the first transistor is electrically connected to the light-emitting element; and
drive modes of the display panel comprise at least a first drive mode, a second drive mode, and a third drive mode, wherein the first drive mode corresponds to a first drive frequency F 1 and a first initialization signal V ref1 , the second drive mode corresponds to a second drive frequency F 2 and a second initialization signal V ref2 , and the third drive mode corresponds to a third drive frequency F 3 and a third initialization signal V ref3 , wherein the driving method comprises:
driving, in the first drive mode, the pixel circuit using the first drive frequency and the first initialization signal;
driving, in the second drive mode, the pixel circuit using the second drive frequency and the second initialization signal; and
driving, in the third drive mode, the pixel circuit using the third drive frequency and the third initialization signal;
wherein F 1 >F 2 >F 3 , and V ref1 ≠V ref2 , V ref1 ≠V ref3 ,
F
2
-
F
3
F
1
-
F
3
≠
❘
"\[LeftBracketingBar]"
V
ref
2
-
V
ref
3
❘
"\[RightBracketingBar]"
❘
"\[LeftBracketingBar]"
V
ref
1
-
V
ref
3
❘
"\[RightBracketingBar]"
.
18. The driving method according to claim 17 , wherein a gate of the first transistor is electrically connected to a scan signal input terminal; and
a switching moment of an initialization signal input to the initialization signal terminal is earlier than a switching moment of a scan signal input to the scan signal input terminal when different drive modes are switched; and a switching moment of an initialization signal corresponding to a current drive mode is within an enable stage of a light emission control signal corresponding to a previous drive mode.
19. A display device, comprising a display panel, wherein the display panel comprises:
a light-emitting element and a pixel circuit electrically connected to the light-emitting element, wherein
the pixel circuit comprises a drive transistor and a first transistor, wherein a first terminal of the drive transistor is electrically connected to a power signal line, a first terminal of the first transistor is electrically connected to an initialization signal line; wherein a second terminal of the first transistor is electrically connected to the drive transistor, or the second terminal of the first transistor is electrically connected to the light-emitting element; and
drive modes of the display panel comprise at least a first drive mode, a second drive mode, and a third drive mode, wherein the first drive mode corresponds to a first drive frequency F 1 and a first initialization signal V ref1 , the second drive mode corresponds to a second drive frequency F 2 and a second initialization signal V ref2 , and the third drive mode corresponds to a third drive frequency F 3 and a third initialization signal V ref3 , wherein F 1 >F 2 >F 3 , V ref1 +V ref2 ,
V
ref
1
≠
V
ref
3
,
F
2
-
F
3
F
1
-
F
3
≠
❘
"\[LeftBracketingBar]"
V
ref
2
-
V
ref
3
❘
"\[RightBracketingBar]"
❘
"\[LeftBracketingBar]"
V
ref
1
-
V
ref
3
❘
"\[RightBracketingBar]"
.
20. The display device according to claim 19 , wherein
F
2
-
F
3
F
1
-
F
3
<
❘
"\[LeftBracketingBar]"
V
ref
2
-
V
ref
3
❘
"\[RightBracketingBar]"
❘
"\[LeftBracketingBar]"
V
ref
1
-
V
ref
3
❘
"\[RightBracketingBar]"
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