Image sensor pixel with deep trench isolation structure

Abstract

An image sensor device is disclosed. The image sensor device includes a substrate having a plurality of pixel regions. The image sensor device also includes a first photodiode in a first pixel region, a source follower transistor coupled to the first photodiode, and a select transistor coupled to the source follower transistor. One of the source follower transistor and the select transistor is in a second pixel region that is different from the first pixel region. While the source follower and the select transistor can be allocated to different cells, either the source follower or the select transistor or both can be further allocated or split into different cells.

What is claimed is: 
     
       1. An image sensor device, comprising:
 a substrate; 
 a plurality of trenches formed in the substrate to define a plurality of pixel regions; 
 a first photodiode in a first pixel region of the plurality of pixel regions; 
 a source follower transistor electrically coupled to the first photodiode; and 
 a select transistor electrically coupled to the source follower transistor and configured to control an electrical connection between an output of the source follower transistor and a bit line associated with the first photodiode, wherein one of the source follower transistor and the select transistor is in a second pixel region of the plurality of pixel regions which is different from the first pixel region, while another one of the source follower transistor and the select transistor is in the first pixel region, 
 wherein at least one of the source follower transistor and the select transistor includes a gate that has a continuous U-shape completely within a boundary of one of the first pixel region or the second pixel region in a plan view of the image sensor device. 
 
     
     
       2. The image sensor device of  claim 1 , wherein the first and second pixel regions are adjacent to each other. 
     
     
       3. The image sensor device of  claim 1 , wherein the source follower transistor includes two sub transistors in two adjacent pixel regions of the plurality of pixel regions, and wherein one of the two adjacent pixel regions is the first pixel region. 
     
     
       4. The image sensor device of  claim 3 , wherein the two sub transistors are connected in series. 
     
     
       5. The image sensor device of  claim 3 , wherein the two sub transistors are connected in parallel. 
     
     
       6. The image sensor device of  claim 1 , wherein the source follower transistor includes four sub transistors in four adjacent pixel regions of the plurality of pixel regions, and wherein one of the four adjacent pixel regions is the first pixel region. 
     
     
       7. The image sensor device of  claim 6 , wherein the four sub transistors include first and second sub transistors connected in series and third and fourth sub transistors connected in series, and wherein the first and second sub transistors are connected in parallel with the third and fourth sub transistors. 
     
     
       8. The image sensor device of  claim 1 , wherein the source follower transistor and the select transistor have different gate oxide thicknesses. 
     
     
       9. The image sensor device of  claim 1 , further comprising:
 a second photodiode in the second pixel region, wherein the first and the second photodiodes share the source follower transistor and the select transistor. 
 
     
     
       10. The image sensor device of  claim 1 , wherein the source follower transistor includes a first gate that has the continuous U-shape in the plan view of the image sensor device, and the select transistor includes a second gate that has another continuous U-shape in the plan view of the image sensor device. 
     
     
       11. The image sensor device of  claim 1 , wherein the gate of the source follower transistor or the select transistor is completely within a boundary of either the first pixel region or the second pixel region without extending beyond the boundary. 
     
     
       12. An image sensor device, comprising:
 a plurality of photodiodes formed in a semiconductor substrate, wherein each photodiode is configured to accumulate photo charges corresponding to an intensity of light received at each photodiode; 
 a plurality of trenches formed in the semiconductor substrate and configured to define a plurality of cells, wherein the cells electrically isolate the photodiodes one from another; 
 a first transistor with a first gate coupled to the accumulated photo charges; and 
 a second transistor with a second gate, wherein a first source/drain region of the first transistor is electrically connected to a second source/drain region of the second transistor through a first source/drain contact physically landing on the first source/drain region, a second source/drain contact physically landing on the second source/drain region, and a metal wiring feature physically connecting the first source/drain contact and the second source/drain contact, wherein the first transistor and the second transistor are in different cells, wherein the metal wiring feature extends across a boundary between the different cells in a plan view of the image sensor device, and 
 wherein the first gate or the second gate has a continuous U-shape completely within the boundary of one of the different cells in the plan view of the image sensor device. 
 
     
     
       13. The image sensor device of  claim 12 , wherein the first transistor is a source follower transistor, and the second transistor is a select transistor. 
     
     
       14. The image sensor device of  claim 12 , wherein the first transistor includes a plurality of sub transistors located in multiple cells. 
     
     
       15. The image sensor device of  claim 12 , wherein the first source/drain region and the second source/drain region have different doping concentrations. 
     
     
       16. The image sensor device of  claim 12 , wherein the trenches extend completely through the semiconductor substrate. 
     
     
       17. The image sensor device of  claim 12 , further comprising:
 a third transistor operable to discharge the accumulated photo charges, wherein the third transistor is in a cell different from where the first and second transistors reside. 
 
     
     
       18. The image sensor device of  claim 12 , wherein the first transistor includes a first channel region, the first source/drain region and the first channel region are different portions of a first active region, and the first active region has another continuous U-shape in the plan view of the image sensor device with a constant width in the different portions. 
     
     
       19. A semiconductor structure, comprising:
 a semiconductor substrate having a first surface and a second surface facing each other; 
 a deep trench isolation (DTI) structure extending from the first surface to the second surface and defining cells isolated from each other; 
 a photoelectric element formed in a first one of the cells, the photoelectric element being configured to receive a light incident at the first surface of the semiconductor substrate; 
 a source follower transistor formed on the second surface of the semiconductor substrate, the source follower transistor sharing the first one of the cells with the photoelectric element; and 
 a select transistor formed on the second surface of the semiconductor substrate, the select transistor being in a second one of the cells different from the first one of the cells, the select transistor configured to control an electrical connection between an output of the source follower transistor and a bit line associated with the photoelectric element; and 
 a dielectric layer disposed on a first gate of the source follower transistor and a second gate of the select transistor, 
 wherein at least one of the first gate and the second gate has an outer surface fully surrounded by and in physical contact with the dielectric layer such that the outer surface in its entirety is completely within a boundary of one of the first one and the second one of the cells in a plan view of the semiconductor structure and has a continuous U-shape in the plan view of the semiconductor structure. 
 
     
     
       20. The semiconductor structure of  claim 19 , further comprising:
 a reset transistor formed on the second surface of the semiconductor substrate, the reset transistor being in a third one of the cells different from the first one and the second one of the cells. 
 
     
     
       21. The semiconductor structure of  claim 19 , further comprising:
 a transfer transistor formed on the second surface of the semiconductor substrate, the transfer transistor sharing the first one of the cells with the photoelectric element. 
 
     
     
       22. The semiconductor structure of  claim 19 , wherein the second one of the cells includes a single transistor that is the select transistor. 
     
     
       23. The semiconductor structure of  claim 19 , wherein the at least one of the first gate and the second gate belongs to the source follower transistor. 
     
     
       24. The semiconductor structure of  claim 19 , wherein the first one of the cells and the second one of the cells are adjacent, and wherein the second one of the cells does not include a second photoelectric element.