US12301659B2ActiveUtilityA1

Inter operating system memory services over communication network connections

64
Assignee: MICRON TECHNOLOGY INCPriority: May 28, 2019Filed: Aug 30, 2022Granted: May 13, 2025
Est. expiryMay 28, 2039(~12.9 yrs left)· nominal 20-yr term from priority
H04L 67/51G06F 12/0223G06F 2212/154G06F 2212/1041G06F 2212/657G06F 12/1009G06F 12/1027G06Q 30/0645H04L 49/9078G06F 13/4234G06F 13/1673G06F 12/1072G06F 3/067G06F 15/17331G06F 12/0866G06F 12/0882G06F 12/0646H04L 67/1097G06Q 50/10
64
PatentIndex Score
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Cited by
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References
18
Claims

Abstract

Systems, methods and apparatuses to provide memory as a service are described. For example, a borrower device is configured to: communicate with a lender device; borrow an amount of memory from the lender device; expand memory capacity of the borrower device for applications running on the borrower device, using at least the local memory of the borrower device and the amount of memory borrowed from the lender device; and service accesses by the applications to memory via communication link between the borrower device and the lender device.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
       1. A device, comprising:
 a first memory; and 
 a processor configured to:
 execute instructions of a first operating system to provide a virtual memory addressable using virtual memory addresses; 
 communicate with an apparatus having a second memory and running a second operating system to borrow the second memory via the second operating system; 
 map a first portion of the virtual memory addresses to physical memory addresses of the first memory in the device, and a second portion of the virtual memory addresses to physical memory addresses of the second memory in the apparatus separate from the device; 
 wherein the processor comprises a microprocessor having a memory management unit configured to convert virtual memory addresses used by the microprocessor into physical memory addresses configured to access the first memory; 
 wherein the processor is further configured to, in response to the translation lookaside buffer or the microprocessor identifying a page fault in accessing a first page of the virtual memory:
 retrieve content of the first page of the virtual memory stored in a second page in the second memory on the apparatus, by running the first operating system to communicate with the second operating system running in the apparatus 
 
 
 
       wherein the memory management unit includes a translation lookaside buffer configured to cache a portion of page tables; and the processor is further configured to, in response to the translation lookaside buffer or the microprocessor identifying a page fault in accessing a first page of the virtual memory:
 retrieve content of the first page of the virtual memory stored in a second page in the second memory on the apparatus, by running the first operating system to communicate with the second operating system running in the apparatus. 
 
     
     
       2. The device of  claim 1 , wherein the processor is further configured to:
 allocate a first page of the virtual memory to an application; 
 map the first page to a second page in the second memory on the apparatus; 
 migrate content of the second page from the second memory on the lender device to a third page in the first memory of the device in response to the application executed in the processor using the first page of the virtual memory; and 
 remap the first page of the virtual memory to the third page in the first memory on the device. 
 
     
     
       3. The device of  claim 2 , wherein the processor is further configured to:
 migrate content of the third page in the first memory on the device to the second page in the second memory on the apparatus, after the first page of the virtual page has not been used for a period of time; and 
 remap the first page of the virtual memory to the second page in the second memory on the apparatus. 
 
     
     
       4. The device of  claim 1 , wherein the memory management unit includes a translation lookaside buffer configured to cache a portion of page tables; and the processor is further configured to, in response to the translation lookaside buffer or the microprocessor identifying a page fault in accessing a first page of the virtual memory:
 allocate a third page in the first memory of the device; 
 store the content, retrieved from the second page in the second memory on the apparatus, in the third page in the first memory; 
 generate a page table entry mapping the first page of the virtual memory to the third page in the first memory; 
 store the page table entry in the page tables in the first memory; and 
 load the page table entry into the translation lookaside buffer to resolve the page fault. 
 
     
     
       5. The device of  claim 4 , wherein the processor is further configured to:
 deallocate the second page after the page table entry is stored in the page tables in the first memory. 
 
     
     
       6. The device of  claim 4 , wherein the processor is further configured to:
 return the second page borrowed from the apparatus after the page table entry is stored in the page tables in the first memory. 
 
     
     
       7. The device of  claim 4 , wherein the processor is further configured to:
 transmit current content of the first page of the virtual memory stored in the third page in the first memory of the device to the second page in the second memory one the apparatus; and 
 update the page table entry to map the first page of the virtual memory to the second page in the second memory on the apparatus. 
 
     
     
       8. The device of  claim 4 , wherein the processor is further configured to:
 allocate a fourth page in the second memory on the apparatus; 
 transmit current content of the first page of the virtual memory stored in the third page in the first memory to the fourth page in the second memory on the apparatus; and 
 update the page table entry to map the first page of the virtual memory to the fourth page in the second memory on the apparatus. 
 
     
     
       9. The device of  claim 4 , wherein the microprocessor and the first memory are configured in a same computer chip. 
     
     
       10. The device of  claim 1 , wherein a portion of the first operating system running in the device is virtualized for execution in the lender device via the second operating system running in the apparatus. 
     
     
       11. The device of  claim 1 , wherein the first operating system running in the device is configured to amount the second memory as a virtual memory device to make available the second memory to applications running in the device. 
     
     
       12. A method, comprising:
 executing, by a processor of a device having a first memory, instructions of a first operating system to provide a virtual memory addressable using virtual memory addresses; 
 communicating, by the device, with an apparatus having a second memory and running a second operating system to borrow the second memory via the second operating system; 
 mapping, by the processor, a first portion of the virtual memory addresses to physical memory addresses of the first memory in the device, and a second portion of the virtual memory addresses to physical memory addresses of the second memory in the apparatus separate from the device; 
 in response to the translation lookaside buffer or the microprocessor identifying a page fault in accessing a first page of the virtual memory:
 retrieving content of the first page of the virtual memory stored in a second page in the second memory on the apparatus, by running the first operating system to communicate with the second operating system running in the apparatus. 
 
 
     
     
       13. The method of  claim 12 , further comprising:
 allocating a first page of the virtual memory to an application; 
 mapping the first page to a second page in the second memory on the apparatus; 
 migrating content of the second page from the second memory on the lender device to a third page in the first memory of the device in response to the application executed in the processor using the first page of the virtual memory; and 
 remapping the first page of the virtual memory to the third page in the first memory on the device. 
 
     
     
       14. The method of  claim 13 , further comprising:
 migrating content of the third page in the first memory on the device to the second page in the second memory on the apparatus, after the first page of the virtual page has not been used for a period of time; and 
 remapping the first page of the virtual memory to the second page in the second memory on the apparatus. 
 
     
     
       15. A non-transitory computer storage medium storing instructions which, when executed on a device having a first memory and a processor, cause the device to perform a method, comprising:
 executing instructions of a first operating system to provide a virtual memory addressable using virtual memory addresses; 
 communicating with an apparatus having a second memory and running a second operating system to borrow the second memory via the second operating system; 
 mapping, a first portion of the virtual memory addresses to physical memory addresses of the first memory in the device, and a second portion of the virtual memory addresses to physical memory addresses of the second memory in the apparatus separate from the device; 
 in response to the translation lookaside buffer or the microprocessor identifying a page fault in accessing a first page of the virtual memory:
 retrieving content of the first page of the virtual memory stored in a second page in the second memory on the apparatus, by running the first operating system to communicate with the second operating system running in the apparatus. 
 
 
     
     
       16. The non-transitory computer storage medium of  claim 15 , wherein the memory management unit includes a translation lookaside buffer configured to cache a portion of page tables; and the method further comprises, in response to the translation lookaside buffer or the microprocessor identifying a page fault in accessing a first page of the virtual memory:
 allocating a third page in the first memory of the device; 
 storing the content, retrieved from the second page in the second memory on the apparatus, in the third page in the first memory; 
 generating a page table entry mapping the first page of the virtual memory to the third page in the first memory; 
 storing the page table entry in the page tables in the first memory; and 
 loading the page table entry into the translation lookaside buffer to resolve the page fault. 
 
     
     
       17. The non-transitory computer storage medium of  claim 16 , further comprising:
 transmitting current content of the first page of the virtual memory stored in the third page in the first memory of the device to the second page in the second memory one the apparatus; and 
 updating the page table entry to map the first page of the virtual memory to the second page in the second memory on the apparatus. 
 
     
     
       18. The non-transitory computer storage medium of  claim 16 , further comprising:
 allocating a fourth page in the second memory on the apparatus; 
 transmitting current content of the first page of the virtual memory stored in the third page in the first memory to the fourth page in the second memory on the apparatus; and 
 updating the page table entry to map the first page of the virtual memory to the fourth page in the second memory on the apparatus.

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