Manufacture of robust, high-performance devices

Abstract

An embodiment relates to a device comprising SiC, the device having a p-shield region that is outside a junction gate field-effect transistor region, wherein a doping concentration in a p-well region within a MOSFET channel is non-uniform. Another embodiment relates to a device comprising SiC, the device having a p-shield region, wherein a doping concentration in a p-well region within a MOSFET channel is non-uniform, wherein at least a portion of the p-shield region is located within the p-well region.

What is claimed is: 
     
       1. A method comprising: forming a silicon carbide (SiC) metal oxide semiconductor field-effect transistor (MOSFET); forming a second conductivity type well region; forming a first conductivity type source region within the second conductivity type well region; forming a MOSFET channel; and forming a second conductivity type shield region in direct contact with a portion of the MOSFET channel along a surface of a drift layer, wherein a lateral location of highest doping concentration of the second conductivity type shield region is positioned within a boundary of the second conductivity type well region, wherein the second conductivity type shield region is located outside the first conductivity type source region, and wherein the MOSFET is a planar MOSFET. 
     
     
       2. The method of  claim 1 , wherein the second conductivity type shield region is located within the second conductivity type well region. 
     
     
       3. The method of  claim 1 , wherein the second conductivity type shield region extends beyond the second conductivity type well region. 
     
     
       4. The method of  claim 1 , wherein the SiC MOSFET is manufactured on SiC epi-wafer comprising a doping ranging from 10 14  to 10 18  cm −3  and a thickness ranging from 1 micrometers (μm) to 300 micrometers (μm). 
     
     
       5. The method of  claim 1 , wherein forming the second conductivity type well region comprises:
 depositing a hard mask comprising one of a silicon dioxide layer, a silicon nitride layer, a polysilicon layer, a silicon oxynitride layer, or a metallic layer with a total thickness ranging from 50 nanometers to 5 micrometers; 
 patterning the hard mask; 
 etching the hard mask; and 
 performing one of an ion-implantation or an epitaxial growth using second conductivity type ions, 
 wherein performing the ion-implantation comprises implanting the second conductivity type ions at energies ranging from 10 keV to 1000 keV, and at implant doses ranging from 10 12  cm −2  to 10 15  cm −2 , and 
 wherein the second conductivity type ions comprise one of aluminum or boron. 
 
     
     
       6. The method of  claim 1 , wherein forming the second conductivity type shield region comprises forming the second conductivity type shield region immediately adjacent to an edge of the second conductivity type well region. 
     
     
       7. The method of  claim 1 , wherein forming the second conductivity type shield region comprises forming the second conductivity type shield region confined within the second conductivity type well region. 
     
     
       8. The method of  claim 1 , wherein forming the second conductivity type shield region comprises forming multiple second conductivity type shield regions in direct contact with the MOSFET channel. 
     
     
       9. The method of  claim 1 , wherein forming the first conductivity type source region comprises forming the first conductivity type source region using one of nitrogen or phosphorus ions. 
     
     
       10. The method of  claim 1 , further comprising:
 forming a gate oxide layer; 
 forming a polysilicon gate layer; 
 forming an interlayer dielectric (ILD) layer; 
 forming a silicide region; and 
 forming an interconnect metal layer. 
 
     
     
       11. The method of  claim 10 , wherein forming the gate oxide layer comprises performing:
 1. one of a thermal oxidation or a chemical vapor deposition (CVD) of a dielectric layer of one of a silicon dioxide layer, a silicon nitride layer, or a silicon oxynitride layer; or 
 2. a stacked combination of the dielectric layer of the silicon dioxide layer, the silicon nitride layer, and the silicon oxynitride layer; 
 wherein the gate oxide layer is formed with a thickness ranging from 10 nanometers to 100 nanometers. 
 
     
     
       12. The method of  claim 10 , wherein forming the polysilicon gate layer comprises depositing a polysilicon layer using one of a plasma-enhanced chemical vapor deposition (PECVD) or a low-pressure chemical vapor deposition (LPCVD) through one of an in-situ doping and a subsequent drive-in doping. 
     
     
       13. The method of  claim 10 , wherein forming the interlayer dielectric (ILD) layer comprises depositing one of:
 1: one of a silicon dioxide layer, a silicon nitride layer, or a silicon oxynitride layer; or 
 2. a stacked combination of the silicon dioxide layer, the silicon nitride layer, and the silicon oxynitride layer; 
 wherein the ILD layer comprises a thickness of at least 50 nanometers. 
 
     
     
       14. The method of  claim 10 , wherein forming the silicide region comprises forming a nickel silicide region on an exposed surface of the SiC. 
     
     
       15. The method of  claim 1 , wherein forming the second conductivity type shield region comprises forming the second conductivity type shield region extending beyond a vertical extent of the second conductivity type well region. 
     
     
       16. A method comprising: forming a silicon carbide (SiC) metal oxide semiconductor field-effect transistor (MOSFET); forming a second conductivity type well region; forming a first conductivity type source region within the second conductivity type well region; forming a MOSFET channel; and
 forming a second conductivity type shield region in direct contact with a portion of the MOSFET channel along a surface of a drift layer, wherein a lateral location of highest doping concentration of the second conductivity type shield region is positioned within a boundary of the second conductivity type well region, wherein the second conductivity type shield region is located outside the first conductivity type source region, wherein a doping concentration in the second conductivity type well region within the MOSFET channel is non-uniform, wherein at least a portion of the second conductivity type shield region is located within the second conductivity type well region, and wherein the MOSFET is a planar MOSFET. 
 
     
     
       17. The method of  claim 16 , wherein the second conductivity type shield region comprises a first region having a doping concentration that is less than a doping concentration of a second region in the lateral location.