Test load circuit

Abstract

A test load circuit includes a test load, a current sensor, and comparator. The test load is connected to a voltage source of a power supply. The current sensor is configured to detect the amount of current flowing through the test load. The comparator has a first input connected to a feedback signal having a voltage associated with the test load current, a second input connected to a command signal having has a voltage associated with a target current through the test load, and an output connected to the test load. The output of the comparator has a voltage that is based on the current difference between the target current and the test load current. The test load has a variable resistance that is controllable by the output of the comparator to adjust the test load current and cause the test load current to match the target current.

What is claimed is: 
     
       1. A test load circuit for testing a power supply comprising:
 a test load configured to be electrically connected to a voltage source of the power supply; 
 a current sensor configured to detect an amount of current flowing through the test load; 
 an amplifier having an input and an output, the input being electrically connected to the test load, the amplifier being configured to amplify a voltage across the current sensor to generate a feedback signal at the output of the amplifier, the voltage across the current sensor being proportional to the test load current such that the voltage of the feedback signal is associated with the test load current; and 
 a processing device including:
 a processing unit configured to generate a command signal having a voltage that is associated with a target current through the test load, and
 a comparator having: 
 a first input electrically connected to the output of the amplifier to receive feedback signal, 
 a second input electrically connected to the processing unit to receive the command signal, and 
 an output electrically connected to the test load, the output having a voltage that is based at least in part on a current difference between the target current and the test load current, 
 
 
 wherein the test load has a variable resistance that is controllable by the output of the comparator, and 
 wherein the processing unit is configured to receive a user input indicative of the target current and to adjust a voltage of the command signal based at least in part on the target current to adjust test load current and cause the test load current to match the target current. 
 
     
     
       2. The test load circuit of  claim 1 , wherein:
 in response to the command signal voltage increasing and indicating that the target current is greater than the test load current, the resistance of the test load decreases such that the test load current increases to match the target current; and 
 in response to the command signal voltage decreasing and indicating that the target current is less than the test load current, the resistance of the test load increases such that the test load current decrease to match the target current. 
 
     
     
       3. The test load circuit of  claim 1 , wherein the command signal voltage is adjustable to modify the comparator output voltage. 
     
     
       4. The test load circuit of  claim 3 , wherein:
 in response to the command signal voltage being modified from a first voltage that is less than the feedback signal voltage to a second voltage that is greater than the feedback signal voltage, the comparator output voltage transitions from a logical low voltage to a logical high voltage; and 
 in response to the command signal voltage being modified from a first voltage that is greater than the feedback signal voltage to a second voltage that is less than the feedback signal voltage, the comparator output voltage transitions from a logical high voltage to a logical low voltage. 
 
     
     
       5. The test load circuit of  claim 3 , wherein the command signal voltage is adjustable to transition the comparator output voltage between a logical high voltage and a logical low voltage. 
     
     
       6. The test load circuit of  claim 5 , wherein in response to the comparator output voltage transitioning between the logical high voltage and the logical low voltage, the resistance of the test load increases or decreases. 
     
     
       7. The test load circuit of  claim 6 , wherein:
 in response to the comparator output voltage transitioning from the logical low voltage to the logical high voltage, the resistance of the test load decreases; and 
 in response to the comparator output voltage transitioning from the logical high voltage to the logical low voltage, the resistance of the test load increases. 
 
     
     
       8. The test load circuit of  claim 6 , wherein in response to the resistance of the test load increasing or decreasing, the test load current increases or decreases. 
     
     
       9. The test load circuit of  claim 8 , wherein:
 in response to the resistance of the test load decreasing, the test load current increases; and 
 in response to the resistance of the test load increasing, the test load current decreases. 
 
     
     
       10. The test load circuit of  claim 8 , wherein in response to the test load current increasing or decreasing, the feedback signal voltage increases or decreases. 
     
     
       11. The test load circuit of  claim 10 , wherein:
 in response to the feedback signal voltage increasing above the command signal voltage, the resistance of the test load increases such that the test load current decreases to match the target current voltage; and 
 in response to the feedback signal voltage decreasing below the command signal voltage, the resistance of the test load decreases such that the test load current increases to match the target current. 
 
     
     
       12. The test load circuit of  claim 1 , wherein the test load is a metal-oxide-semiconductor field-effect transistor (MOSFET), the MOSFET including a gate that is electrically connected to the output of the comparator such that the output of the comparator is controllable to adjust the resistance of the MOSFET. 
     
     
       13. The test load circuit of  claim 1 , further comprising a temperature sensor electrically connected to the processing device and electrically isolated from the test load and the comparator of the processing device, the temperature sensor being positioned adjacent to the test load and configured to monitor a temperature of the test load, the processing unit being configured to decrease the command signal voltage in response to the test load temperature being greater than a threshold temperature. 
     
     
       14. The test load circuit of  claim 1 , wherein the voltage source has a known voltage, and wherein the target current is determined based on the voltage of the voltage source and a target power dissipation of the test load. 
     
     
       15. A method for adjusting an amount of current flowing through a test load, the method comprising:
 receiving, via a processing device, user input indicative of a target current through the test load; 
 adjusting, using the processing device, a voltage of a command signal based at least in part on the target current; 
 determining a voltage across a current sensor that is electrically connected to the test load, the current sensor voltage being associated with the test load current; 
 amplifying the current sensor voltage to generate the feedback signal; 
 receiving a feedback signal, the feedback signal having a voltage that is associated with the test load current; 
 comparing, via a comparator of the processing device, the command signal voltage to the feedback signal voltage; 
 in response to the command signal voltage being greater than the feedback signal voltage, causing the test load current to increase; and 
 in response to the command signal voltage being less than the feedback signal voltage, causing the test load current to decrease. 
 
     
     
       16. The method of  claim 15 , wherein causing the test load current to increase includes increasing a voltage applied to the test load to cause a resistance of the test load to decrease. 
     
     
       17. The method of  claim 15 , wherein causing the test load current to decrease includes decreasing a voltage applied to the test load to cause a resistance of the test load to increase. 
     
     
       18. The method of  claim 17 , further comprising:
 generating, via a temperature sensor that is electrically connected to the processing device and electrically isolated from the test load and the comparator of the processing device, a temperature of the test load; and 
 in response to the temperature of the test load being greater than a threshold temperature, decreasing, via the processing device, the command signal voltage.