Semiconductor device

Abstract

A semiconductor device is provided. The semiconductor device includes: first, second and third active patterns on a logic cell region of a substrate and are spaced apart from each other in a first direction; first and second gate electrodes, the first gate electrode crossing the first active pattern and the second gate electrode crossing the second active pattern; a first separation pattern provided between the first and second active patterns; a second separation pattern provided between the second and third active patterns; a first gate insulating layer interposed between the first gate electrode and the first active pattern; and a first gate cutting pattern interposed between the first and second gate electrodes, and in contact with a top surface of the first separation pattern. The first separation pattern is wider than the second separation pattern, and the first gate insulating layer extends between the first gate electrode and the first separation pattern, and contacts side and top surfaces of the first separation pattern.

What is claimed is: 
     
       1. A semiconductor device, comprising:
 a first active pattern, a second active pattern, and a third active pattern, which are provided on a logic cell region of a substrate and are spaced apart from each other in a first direction; 
 a first gate electrode and a second gate electrode, which are aligned with each other along the first direction, the first gate electrode crossing the first active pattern and the second gate electrode crossing the second active pattern; 
 a first separation pattern provided between the first active pattern and the second active pattern, wherein a bottom surface of the first separation pattern has a curved profile; 
 a second separation pattern provided between the second active pattern and the third active pattern; 
 a first gate insulating layer interposed between the first gate electrode and the first active pattern; 
 a first gate cutting pattern, which is interposed between the first gate electrode and the second gate electrode and is in contact with a top surface of the first separation pattern; and 
 a device isolation layer, which is provided on the substrate to define the first active pattern and the second active pattern, wherein the first separation pattern penetrates an upper portion of the device isolation layer, 
 wherein a largest width of the first separation pattern along the first direction is larger than a largest width of the second separation pattern along the first direction, and 
 wherein the first gate insulating layer extends between the first gate electrode and the first separation pattern, and is in contact with side and top surfaces of the first separation pattern. 
 
     
     
       2. The semiconductor device of  claim 1 , wherein the first gate insulating layer extends between the first gate electrode and the first gate cutting pattern, and is in contact with a lower side surface of the first gate cutting pattern. 
     
     
       3. The semiconductor device of  claim 1 , further comprising a second gate insulating layer interposed between the second active pattern and the second gate electrode,
 wherein the second gate insulating layer extends between the second gate electrode and the first separation pattern, and between the second gate electrode and the second separation pattern, and 
 wherein the second gate insulating layer is in contact with side and top surfaces of the first separation pattern, and side and top surfaces of the second separation pattern. 
 
     
     
       4. The semiconductor device of  claim 1 , wherein a smallest width of the first gate cutting pattern along the first direction is different from a largest width of the first separation pattern along the first direction. 
     
     
       5. The semiconductor device of  claim 1 , wherein a distance along the first direction between the first separation pattern and the first active pattern is substantially equal to a distance along the first direction between the first separation pattern and the second active pattern. 
     
     
       6. The semiconductor device of  claim 1 , wherein a distance along the first direction between the first separation pattern and the first active pattern is substantially equal to a distance along the first direction between the second separation pattern and the second active pattern. 
     
     
       7. The semiconductor device of  claim 1 , wherein the semiconductor device comprises a fourth active pattern and a fifth active pattern, which are provided on a peripheral region of the substrate and are spaced apart from each other in the first direction,
 wherein each of the first to third active patterns comprises semiconductor patterns, which are stacked in an upper portion thereof to be spaced apart from each other along a third direction perpendicular to an upper surface of the substrate, 
 wherein a peripheral channel pattern is provided in each of the fourth active pattern and the fifth active pattern, and 
 wherein the peripheral channel pattern comprises semiconductor patterns, which are vertically stacked, and sacrificial layers, which are respectively interposed between the semiconductor patterns. 
 
     
     
       8. The semiconductor device of  claim 7 , further comprising a third separation pattern provided between the fourth active pattern and the fifth active pattern,
 wherein a largest width of the third separation pattern along the first direction is larger than a largest width of the second separation pattern along the first direction. 
 
     
     
       9. The semiconductor device of  claim 7 , further comprising:
 a peripheral gate electrode crossing the fourth active pattern; and 
 a peripheral gate insulating layer provided between the peripheral gate electrode and the peripheral channel pattern, 
 wherein the peripheral gate insulating layer comprises:
 an oxide layer provided on the peripheral channel pattern; and 
 a high-k dielectric layer provided on the oxide layer, and 
 
 wherein the oxide layer is conformally provided on top and side surfaces of the peripheral channel pattern. 
 
     
     
       10. A semiconductor device, comprising:
 a substrate comprising a peripheral region and a logic cell region; 
 a first active pattern and a second active pattern, which are provided on the logic cell region and are spaced apart from each other in a first direction; 
 a device isolation layer provided on the substrate between the first active pattern and the second active pattern; 
 a first gate electrode and a second gate electrode, which are aligned with each other along the first direction, the first active pattern crossing the first active pattern and the second gate electrode crossing the second active pattern; 
 a third active pattern provided on the peripheral region, the third active pattern comprising a peripheral channel pattern provided in an upper portion thereof; 
 a peripheral gate electrode crossing the third active pattern; 
 a peripheral gate insulating layer provided between the peripheral gate electrode and the peripheral channel pattern, the peripheral gate insulating layer comprising an oxide layer provided on the peripheral channel pattern and a high-k dielectric layer provided on the oxide layer; 
 a first separation pattern provided between the first active pattern and the second active pattern, and penetrating an upper portion of the device isolation layer; and 
 a gate cutting pattern interposed between the first gate electrode and the second gate electrode, and contacting the first separation pattern, 
 wherein the oxide layer is conformally provided on top and side surfaces of the peripheral channel pattern, and 
 wherein a bottom surface of the first separation pattern has a convex profile toward the device isolation layer. 
 
     
     
       11. The semiconductor device of  claim 10 , further comprising:
 a fourth active pattern, which is provided on the logic cell region and is spaced apart from the second active pattern in the first direction, a distance between the first active pattern and the second active pattern along the first direction being larger than a distance between the second active pattern and the fourth active pattern along the first direction; and 
 a second separation pattern provided between the second active pattern and the fourth active pattern, 
 wherein a largest width of the first separation pattern along the first direction is larger than a largest width of the second separation pattern along the first direction. 
 
     
     
       12. The semiconductor device of  claim 11 , further comprising:
 a fifth active pattern, which is provided on the peripheral region and is spaced apart from the third active pattern in the first direction; and 
 a third separation pattern provided between the third active pattern and the fifth active pattern, 
 wherein a largest width of the third separation pattern along the first direction is larger than a largest width of the second separation pattern along the first direction. 
 
     
     
       13. The semiconductor device of  claim 11 , wherein a distance between the first separation pattern and the first active pattern along the first direction is substantially equal to a distance between the second separation pattern and the second active pattern along the first direction. 
     
     
       14. The semiconductor device of  claim 10 , wherein a smallest width of the gate cutting pattern along the first direction is different from a largest width of the first separation pattern along the first direction. 
     
     
       15. A semiconductor device, comprising:
 a substrate comprising a logic cell region; 
 a first active pattern, a second active pattern, and a third active pattern, which are provided on the logic cell region and are spaced apart from each other in a first direction; 
 a device isolation layer provided on the substrate between the first active pattern and the second active pattern, and between the second active pattern and the third active pattern; 
 a pair of first source/drain patterns provided on the first active pattern, a pair of second source/drain patterns provided on the second active pattern, and a pair of third source/drain patterns provided on the third active pattern; 
 a first channel pattern provided between the pair of first source/drain patterns, a second channel pattern provided between the pair of second source/drain patterns, and a third channel pattern provided between the pair of third source/drain patterns; 
 a first gate electrode provided on the first channel pattern; 
 a second gate electrode provided on the second channel pattern; 
 a first gate insulating layer interposed between the first channel pattern and the first gate electrode; 
 a second gate insulating layer interposed between the second channel pattern and the second gate electrode; 
 a first pair of gate spacers provided on sides of the first gate electrode and a second pair of gate spacers provided on sides of the second gate electrode; 
 a gate capping pattern provided on the first gate electrode and the second gate electrode; 
 a first separation pattern provided between the first active pattern and the second active pattern, and penetrating a first upper portion of the device isolation layer; 
 a second separation pattern provided between the second active pattern and the third active pattern, and penetrating a second upper portion of the device isolation layer; 
 a first interlayer insulating layer provided on the gate capping pattern; 
 a first gate cutting pattern, which is interposed between the first gate electrode and the second gate electrode, penetrates the gate capping pattern and is in contact with a top surface of the first separation pattern; 
 an active contact, which penetrates the first interlayer insulating layer and is electrically connected to one of the first to third source/drain patterns; 
 a gate contact, which penetrates the first interlayer insulating layer and the gate capping pattern, and is electrically connected to one of the first and second gate electrodes; 
 a second interlayer insulating layer provided on the first interlayer insulating layer; 
 a first metal layer, which is provided in the second interlayer insulating layer and is electrically connected to the active contact; and 
 a second metal layer provided on the first metal layer, 
 wherein a largest width of the first separation pattern along the first direction is larger than a largest width of the second separation pattern along the first direction, and 
 wherein the first gate insulating layer extends between the first gate electrode and the first separation pattern, and is in contact with side and top surfaces of the first separation pattern. 
 
     
     
       16. The semiconductor device of  claim 15 , wherein the first gate insulating layer extends between the first gate electrode and the first gate cutting pattern, and is in contact with a lower side surface of the first gate cutting pattern. 
     
     
       17. The semiconductor device of  claim 15 , wherein a bottom surface of the first separation pattern has a curved profile. 
     
     
       18. The semiconductor device of  claim 15 , wherein a ratio of a distance between the second separation pattern and the second channel pattern along the first direction to a distance between the first separation pattern and the first channel pattern along the first direction ranges from 0.9 to 1.1. 
     
     
       19. The semiconductor device of  claim 15 , wherein the semiconductor device further comprises:
 a fourth active pattern and a fifth active pattern, which are provided on a peripheral region of the substrate and are spaced apart from each other in the first direction; 
 a third separation pattern provided between the fourth active pattern and the fifth active pattern; and 
 a second gate cutting pattern in contact with a top surface of the third separation pattern, and 
 wherein a largest width of the third separation pattern along the first direction is larger than a largest width of the second separation pattern along the first direction.