US12328888B2ActiveUtilityA1

Method of manufacturing semiconductor device

60
Assignee: SUMITOMO ELECTRIC INDUSTRIESPriority: Jan 24, 2022Filed: Oct 18, 2022Granted: Jun 10, 2025
Est. expiryJan 24, 2042(~15.5 yrs left)· nominal 20-yr term from priority
Inventors:Yukihiro Tsuji
H10P 95/70H10P 52/00H10P 50/20H10P 76/403H10D 64/01H10D 62/161H10D 30/4755H10D 62/149H10D 30/015H10D 62/8503
60
PatentIndex Score
0
Cited by
4
References
10
Claims

Abstract

A method of manufacturing a semiconductor device includes: forming an electron transit layer; forming an electron supply layer; forming a protective film; forming a zinc oxide film; forming a sacrifice layer; forming a first opening and a second opening in the sacrifice layer and the zinc oxide film; forming a third opening connecting to the first opening and a fourth opening connecting to the second opening; forming, by acid treatment using a weakly acidic solution, a first gap in a first portion exposed to the first opening of the zinc oxide film, and a second gap in a second portion exposed to the second opening of the zinc oxide film; forming, after the acid treatment, a source region on a bottom surface of the third opening and a drain region on a bottom surface of the fourth opening; and removing the zinc oxide film.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
       1. A method of manufacturing a semiconductor device comprising:
 forming an electron transit layer above a substrate; 
 forming an electron supply layer above the electron transit layer; 
 forming a protective film above the electron transit layer; 
 forming a zinc oxide film above the protective film; 
 forming a sacrifice layer above the zinc oxide film; 
 forming a first opening and a second opening in the sacrifice layer and the zinc oxide film; 
 forming a third opening connecting to the first opening and a fourth opening connecting to the second opening in the protective film, the electron supply layer, and the electron transit layer; 
 forming, by acid treatment using a weakly acidic solution, a first gap in a first portion exposed to the first opening of the zinc oxide film, and a second gap in a second portion exposed to the second opening of the zinc oxide film; 
 forming, after the acid treatment, a source region containing a first conductive impurity on a bottom surface of the third opening and a drain region containing the first conductive impurity on a bottom surface of the fourth opening; and 
 removing the zinc oxide film after forming the source region and the drain region. 
 
     
     
       2. The method of manufacturing a semiconductor device according to  claim 1 , wherein pH of the weakly acidic solution is 3.0 or more and less than 7.0. 
     
     
       3. The method of manufacturing a semiconductor device according to  claim 1 , wherein pH of the weakly acidic solution is 6.86. 
     
     
       4. The method of manufacturing a semiconductor device according to  claim 1 , wherein the weakly acidic solution contains phosphoric acid. 
     
     
       5. The method of manufacturing a semiconductor device according to  claim 1 , wherein forming the third opening and the fourth opening are performed before the acid treatment. 
     
     
       6. The method of manufacturing a semiconductor device according to  claim 1 , wherein the acid treatment is performed before forming the third opening and the fourth opening. 
     
     
       7. The method of manufacturing a semiconductor device according to  claim 6 , wherein the weakly acidic solution contains sodium hydroxide. 
     
     
       8. The method of manufacturing a semiconductor device according to  claim 1 , wherein a silicon nitride film is formed as the protective film. 
     
     
       9. The method of manufacturing a semiconductor device according to  claim 1 , wherein an aluminum oxide film or a silicon nitride film is famed as the sacrifice layer. 
     
     
       10. The method of manufacturing a semiconductor device according to  claim 1 , wherein a concentration of the first conductive impurity in each of the source region and the drain region is 5×10 18  cm −3  or more and 2×10 19  cm −3  or less.

Cited by (0)

No later patents cite this yet.

References (0)

No backward citations on record.