Unlimited bandwidth shifting systems and methods of an all-digital phase locked loop

Abstract

This disclosure is directed towards systems and methods that improve bandwidth shifting operations of an ADPLL without losing a lock of the ADPLL and having the benefit of being able to change the bandwidth an unlimited amount of times. Indeed, a processor may transmit amplification parameters to the ADPLL to implement a bandwidth shift. The shift may occur in response to a enable signal, such as a gear trigger control signal (gear_retime signal) or a enable signal generated to cause alignment of the shifting with a clock signal (e.g., enable signal generated by AND logic gates). These systems and methods described herein many enable multiple bandwidth changing operations to occur without compromising the complexity and footprint of the system.

What is claimed is: 
     
       1. An electronic device, comprising:
 processing circuitry configured to generate a first input signal and a plurality of amplification parameters; and 
 a digital loop filter configured to generate a first output signal based at least on the first input signal and the plurality of amplification parameters, the digital loop filter comprising synchronization circuitry configured to align the first output signal with a clock signal via transmitting a first amplification parameter of the plurality of amplification parameters based on the clock signal and an enable signal. 
 
     
     
       2. The electronic device of  claim 1 , wherein the synchronization circuitry comprises first synchronization circuitry and second synchronization circuitry, wherein the digital loop filter comprises:
 a first path comprising the first synchronization circuitry and a first multiplier; and 
 a second path comprising the second synchronization circuitry and a second multiplier. 
 
     
     
       3. The electronic device of  claim 2 , wherein the plurality of amplification parameters comprises the first amplification parameter and a second amplification parameter, wherein the digital loop filter is configured to generate the first output signal at least in part by:
 receiving the first amplification parameter via the second multiplier; 
 receiving the second amplification parameter via the first multiplier; 
 receiving a second output signal via a feedback path of the digital loop filter; and 
 generating the first output signal based at least on the first input signal, the first amplification parameter, the second output signal, and the second amplification parameter. 
 
     
     
       4. The electronic device of  claim 3 , wherein the second output signal is generated based at least on the first multiplier being loaded with the first amplification parameter and the second multiplier being loaded with a third amplification parameter. 
     
     
       5. The electronic device of  claim 1 , wherein the digital loop filter comprises a first path comprising a first multiplier coupled to first synchronization circuitry, and wherein the first multiplier is configured to be loaded, at a first time, with the first amplification parameter of the plurality of amplification parameters via a first set of flip-flops. 
     
     
       6. The electronic device of  claim 5 , wherein the digital loop filter comprises a second path comprising a second multiplier coupled to second synchronization circuitry, and wherein the second multiplier is configured to be loaded, at a second time, with the first amplification parameter via the first set of flip-flops. 
     
     
       7. The electronic device of  claim 6 , wherein the digital loop filter is configured to generate the first output signal based at least on the first input signal and the plurality of amplification parameters by:
 at the first time, generating a second output signal based at least on a second input signal, the first multiplier loaded with the first amplification parameter of the plurality of amplification parameters, and the second multiplier loaded with a second amplification parameter of the plurality of amplification parameters, and 
 at the second time, generating the first output signal based at least on the first input signal, the second output signal, the second multiplier loaded with the first amplification parameter, and the first multiplier loaded with a third amplification parameter of the plurality of amplification parameters. 
 
     
     
       8. The electronic device of  claim 1 , wherein the synchronization circuitry is configured to align the first output signal with the clock signal based at least on the enable signal from a logic gate. 
     
     
       9. The electronic device of  claim 8 , wherein the synchronization circuitry comprises a first flip-flop and a second flip-flop, wherein the logic gate comprises an inverted input and a non-inverted input, the inverted input being coupled to an output of the first flip-flop, the non-inverted input being coupled to an input of the first flip-flop, and the second flip-flop is configured to receive the enable signal from the logic gate. 
     
     
       10. An electronic device, comprising:
 processing circuitry configured to generate a first input signal, a second input signal, a first amplification parameter, a second amplification parameter, a third amplification parameter, and a clock signal; and 
 a digital loop filter configured to transmit:
 at a first time, a first output signal based at least on the first input signal, the first amplification parameter, and the second amplification parameter; and 
 at a second time, a second output signal based at least on the second input signal, the second amplification parameter, and the third amplification parameter, wherein the digital loop filter comprises synchronization circuitry configured to align the first output signal and the second output signal with transitions of the clock signal. 
 
 
     
     
       11. The electronic device of  claim 10 , wherein the processing circuitry is configured to:
 send the first input signal to the digital loop filter of a phase locked loop; 
 send the first amplification parameter to the digital loop filter; 
 send the clock signal to the digital loop filter; and 
 send the second amplification parameter to the digital loop filter, wherein a first set of flip-flops of the digital loop filter are configured to store the second amplification parameter over the first amplification parameter based at least on a first transition of the clock signal. 
 
     
     
       12. The electronic device of  claim 10 , comprising a phase locked loop associated with the digital loop filter, wherein the processing circuitry is configured to change a bandwidth of the phase locked loop at least three times based at least on generating the first amplification parameter, the second amplification parameter, and the third amplification parameter. 
     
     
       13. The electronic device of  claim 10 , wherein the second output signal is generated based at least on the second input signal, the first output signal, the second amplification parameter, and the third amplification parameter. 
     
     
       14. The electronic device of  claim 10 , wherein the digital loop filter comprises an adder and a feedback path, wherein the feedback path is configured to send the first output signal to the adder via one or more flip-flops, wherein the adder is configured to combine the first output signal and an intermediate output signal to generate the second output signal based at least on a transition of the clock signal. 
     
     
       15. A method comprising:
 sending, via processing circuitry, a first input signal to a digital loop filter of a phase locked loop; 
 sending, via the processing circuitry, a first amplification parameter to the digital loop filter; 
 sending, via the processing circuitry, a clock signal to the digital loop filter, wherein the digital loop filter comprises synchronization circuitry configured to align operations of the digital loop filter with the clock signal; and 
 sending, via the processing circuitry, a second amplification parameter to the digital loop filter, wherein a first flip-flop is configured to store the second amplification parameter over the first amplification parameter based at least on a first transition of the clock signal. 
 
     
     
       16. The method of  claim 15 , comprising sending, via the processing circuitry, a third amplification parameter to the digital loop filter, wherein the first flip-flop is configured to store the third amplification parameter. 
     
     
       17. The method of  claim 15 , comprising
 causing, via the processing circuitry, a transceiver to communicate using a first bandwidth based at least on the first amplification parameter, wherein the transceiver comprises the phase locked loop and the digital loop filter; and 
 causing, via the processing circuitry, the transceiver to communicate using a second bandwidth based at least on the second amplification parameter. 
 
     
     
       18. The method of  claim 15 , comprising sending, via the processing circuitry, a second transition in the clock signal to a second flip-flop of the digital loop filter to cause the second flip-flop to store the second amplification parameter. 
     
     
       19. The method of  claim 15 , comprising retiming, via the processing circuitry, the synchronization circuitry of the digital loop filter. 
     
     
       20. The electronic device of  claim 1 , wherein the synchronization circuitry comprises logic circuitry that receives the clock signal and the enable signal.