Unit capacitor-based ramp analog-to-digital converter

Abstract

A method to operate an analog to digital converter. The method may storing a sampled signal of an input voltage on capacitors, of an up ramp generator and of a down ramp generator to obtain a sampled signal, enabling one of the up ramp generator and the down ramp generator based on a sign of the sampled signal, detecting, on the capacitors, a zero crossing of a stepped ramp that is generated in the one of the up ramp generator and the down ramp generator, and generating a digital representation of the sampled signal based on a number of steps in the stepped ramp.

What is claimed is: 
     
       1. A method comprising:
 storing a sampled signal of an input voltage on capacitors of an up ramp generator and of a down ramp generator; 
 enabling one of the up ramp generator and the down ramp generator based on a sign of the sampled signal; 
 detecting, on the capacitors, a zero crossing of a stepped ramp that is generated in the one of the up ramp generator and the down ramp generator; and 
 generating a digital representation of the sampled signal based on a number of steps in the stepped ramp. 
 
     
     
       2. The method of  claim 1 , wherein the capacitors comprise an array of unit value capacitors. 
     
     
       3. The method of  claim 1 , further comprising enabling the one of the up ramp generator and the down ramp generator by enabling a plurality of inverters connected in series in the one of the up ramp generator and the down ramp generator. 
     
     
       4. The method of  claim 3 , further comprising initiating the stepped ramp by triggering a first inverter in the plurality of inverters connected in series. 
     
     
       5. The method of  claim 3 , further comprising generating the digital representation of the sampled signal by detecting states of respective inverters in the plurality of inverters, after detecting the zero crossing. 
     
     
       6. The method of  claim 1 , wherein detecting the zero crossing comprises monitoring a voltage across first plates of a plurality of unit value capacitors on which the sampled signal is initially stored. 
     
     
       7. The method of  claim 1 , further comprising determining the sign of the sampled signal using a comparator. 
     
     
       8. The method of  claim 1 , further comprising converting the digital representation of the sampled signal with a thermo-to-gray converter. 
     
     
       9. The method of  claim 8 , further comprising converting an output of the thermo-to-gray converter with a gray-to-binary converter. 
     
     
       10. The method of  claim 1 , further comprising not enabling another of the one of the up ramp generator and the down ramp generator. 
     
     
       11. A method comprising:
 receiving a signal to be sampled as a sampled signal; 
 storing the sampled signal across first plates of multiple capacitors; 
 triggering a first one of a string of series-connected inverters, wherein second plates of the multiple capacitors are respectively connected to outputs of every second series-connected inverter among the string of series-connected inverters; 
 detecting a zero crossing of a stepped ramp generated in coordination with the multiple capacitors and the string of series-connected inverters; and 
 generating a digital representation of the sampled signal that is based on a number of steps in the stepped ramp. 
 
     
     
       12. The method of  claim 11 , wherein the multiple capacitors comprise an array of unit value capacitors. 
     
     
       13. The method of  claim 11 , further comprising generating the digital representation of the sampled signal by detecting states of respective inverters in the string of series-connected inverters, after detecting the zero crossing. 
     
     
       14. The method of  claim 11 , wherein detecting the zero crossing comprises monitoring a voltage across the first plates of the multiple capacitors on which the sampled signal is initially stored. 
     
     
       15. The method of  claim 11 , wherein the multiple capacitors are unit value capacitors. 
     
     
       16. The method of  claim 11 , further comprising converting the digital representation of the sampled signal with a thermo-to-gray converter. 
     
     
       17. The method of  claim 16 , further comprising converting an output of the thermo-to-gray converter with a gray-to-binary converter. 
     
     
       18. A device comprising:
 an up ramp generator; 
 a down ramp generator; 
 a first sampling switch and a second sampling switch respectively connected to an input of the up ramp generator and to an input of the down ramp generator; and 
 a comparator in communication with each of the up ramp generator and the down ramp generator, the comparator configured to trigger operation of one of the up ramp generator and the down ramp generator, 
 wherein each of the up ramp generator and the down ramp generator is configured, upon being triggered by the comparator, to:
 detect a zero crossing of a stepped ramp that is generated in the one of the up ramp generator and the down ramp generator; and 
 generate a digital representation of a sampled signal based on a number of steps in the stepped ramp. 
 
 
     
     
       19. The device of  claim 18 , wherein each of the up ramp generator and the down ramp generator comprises an array of unit value capacitors on which a sampled signal, delivered via the first sampling switch and a second sampling switch, is stored. 
     
     
       20. The device of  claim 18 , wherein each of the up ramp generator and the down ramp generator comprises a plurality of inverters connected in series and from which the digital representation of the sampled signal is taken, after the zero crossing is detected.