Systems and methods for clock gating

Abstract

Described are systems and methods for clock gating components on a system-on-chip. A processing system includes one or more cores, each core including a clock gating enable bit register which is set by software when an expected idle period of the core meets or exceeds a clock gating threshold, and a power management unit connected to the one or more cores. The power management unit configured to receive an idle notification from a core of the one or more cores and initiate clock gating a clock associated with the core when the core and additional logic is quiescent and the clock gating enable bit register is set. The clock gating threshold is a defined magnitude greater than a clock wake-up time.

What is claimed is: 
     
       1. A processing system comprising:
 one or more cores, each core including a clock gating enable bit register which is set when an expected idle period of the core meets or exceeds a clock gating threshold; and 
 a power management unit connected to the one or more cores, wherein the power management unit is configured to:
 receive an idle notification from a core of the one or more cores; and 
 initiate clock gating a clock associated with the core of the one or more cores when the core of the one or more cores and additional logic is quiescent and the clock gating enable bit register is set, 
 
 wherein the clock gating threshold is a defined magnitude greater than a clock wake-up time. 
 
     
     
       2. The processing system of  claim 1 , wherein the clock gating threshold is based on frequency of idle state to non-idle state on a per core basis. 
     
     
       3. The processing system of  claim 1 , wherein the clock gating threshold is dynamically set based on performance. 
     
     
       4. The processing system of  claim 1 , wherein the clock gating enable bit register is a configuration and status register. 
     
     
       5. The processing system of  claim 1 , wherein the power management unit is further configured to reenable the clock associated with the core of the one or more cores when activity is detected for the clock. 
     
     
       6. The processing system of  claim 1 , wherein the power management unit includes an activity monitor for each of the one or more cores, each activity monitor is configured to detect activity in an associated core and signal the power management unit to reenable an associated clock. 
     
     
       7. The processing system of  claim 1 , wherein the clock gating enable bit register is set by software. 
     
     
       8. The processing system of  claim 7 , wherein the software is configured to monitor idle or sleep states to determine the expected idle period. 
     
     
       9. The processing system of  claim 7 , wherein the software is configured to count idle cycles to determine the expected idle period. 
     
     
       10. The processing system of  claim 7 , wherein the software is configured to use knowledge of an expected wake-up time after initiating an idle or sleep state to determine the expected idle period. 
     
     
       11. The processing system of  claim 7 , wherein the software is configured to use a predictor of idle or sleep times to determine the expected idle period. 
     
     
       12. The processing system of  claim 11 , wherein the predictor is configured to use a counter to provide hysteresis to account for past events. 
     
     
       13. The processing system of  claim 1 , wherein the clock gating enable bit register is set by the power management unit. 
     
     
       14. The processing system of  claim 1 , wherein the power management unit includes a clock gating controller to initiate clock gating by an associated clock controller. 
     
     
       15. The processing system of  claim 1 , further comprising:
 one or more bus blockers configured to signal the power management unit when the core of the one or more cores and additional logic is quiescent. 
 
     
     
       16. A method comprising:
 setting, by a processing system component, a clock gating enable bit for a core when an expected idle period of the core meets or exceeds a clock gating threshold; 
 receiving, by power management unit, an idle indication from the core; and 
 initiating, by the power management unit, clock gating of a clock associated with the core when the core and additional logic are quiescent and the clock gating enable bit is set, 
 wherein the clock gating threshold is a defined magnitude greater than a clock wake-up time. 
 
     
     
       17. The method of any of  claim 16 , further comprising:
 detecting, by an activity monitor, an activity in the core; and 
 signaling, the power management unit by the activity monitor based on the activity, to reenable the clock. 
 
     
     
       18. The method of  claim 16 , further comprising:
 using, by the processing system component, knowledge of an expected wake-up time after initiating an idle or sleep state to determine the expected idle period. 
 
     
     
       19. The method of  claim 16 , further comprising:
 notifying, the power management unit by bus blockers, when the core and the additional logic is quiescent. 
 
     
     
       20. A non-transitory computer readable medium comprising a circuit representation that, when processed by a computer, is used to program or manufacture an integrated circuit comprising:
 one or more cores, each core including a clock gating enable bit register which is set when an expected idle period of the core meets or exceeds a clock gating threshold; and 
 a power management unit connected to the one or more cores, wherein the power management unit is configured to:
 receive an idle notification from a core of the one or more cores; and 
 initiate clock gating a clock associated with the core of the one or more cores when the core of the one or more cores and additional logic is quiescent and the clock gating enable bit register is set, 
 
 wherein the clock gating threshold is a defined magnitude greater than a clock wake-up time.