US12349396B2ActiveUtilityPatentIndex 63

Semiconductor device with shallow contacts and method for fabricating the same

Assignee: NANYA TECHNOLOGY CORPPriority: Aug 29, 2022Filed: Aug 29, 2022Granted: Jul 1, 2025

Est. expiryAug 29, 2042(~16.2 yrs left)· nominal 20-yr term from priority

H10W 20/42H10W 20/0698H10W 20/056H10W 20/43H10D 64/513H10D 64/252H10D 64/01H10D 30/60H10B 12/488H10B 12/01H10D 30/63H10D 64/027H01L 23/5226

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Claims

Abstract

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a word line structure positioned in the substrate; a plurality of impurity regions positioned in the substrate and adjacent to the word line structure; a plurality of bottom shallow contacts positioned on the word line structure; a first interconnect layer positioned on the plurality of bottom shallow contacts; a plurality of top shallow contacts positioned on the first interconnect layer; and a plurality of deep contacts positioned on the plurality of impurity regions. Top surfaces of the plurality of top shallow contacts and top surfaces of the plurality of deep contacts are substantially coplanar.

Claims

exact text as granted — not AI-modified

What is claimed is:

1. A semiconductor device, comprising:
a substrate;
a word line structure positioned in the substrate;
a plurality of impurity regions positioned in the substrate and adjacent to the word line structure;
a plurality of bottom shallow contacts positioned on the word line structure;
a first interconnect layer positioned on the plurality of bottom shallow contacts;
a plurality of top shallow contacts positioned on the first interconnect layer; and
a plurality of deep contacts positioned on the plurality of impurity regions;
wherein top surfaces of the plurality of top shallow contacts and top surfaces of the plurality of deep contacts are substantially coplanar.

2. The semiconductor device of claim 1 , wherein widths of the plurality of bottom shallow contacts are less than widths of the plurality of deep contacts.

3. The semiconductor device of claim 2 , wherein the word line structure comprises:
a word line insulating layer inwardly positioned in the substrate and comprising a U-shaped cross-sectional profile;
a word line conductive layer positioned on the word line insulating layer; and
a word line capping layer positioned on the word line insulating layer and the word line conductive layer;
wherein the plurality of bottom shallow contacts are positioned along the word line capping layer and positioned on the word line conductive layer.

4. The semiconductor device of claim 3 , wherein a width of the word line structure and a width of the first interconnect layer are different.

5. The semiconductor device of claim 3 , wherein a width of the word line structure and a width of the first interconnect layer are substantially the same.

6. The semiconductor device of claim 4 , wherein the widths of the plurality of bottom shallow contacts and widths of the plurality of top shallow contacts are substantially the same.

7. The semiconductor device of claim 4 , wherein the widths of the plurality of bottom shallow contacts and widths of the plurality of top shallow contacts are different.

8. The semiconductor device of claim 4 , wherein the widths of the plurality of bottom shallow contacts are substantially the same.

9. The semiconductor device of claim 4 , wherein the widths of the plurality of bottom shallow contacts are different.

10. The semiconductor device of claim 4 , wherein widths of the plurality of top shallow contacts are substantially the same.

11. The semiconductor device of claim 4 , widths of the plurality of top shallow contacts are different.

12. The semiconductor device of claim 4 , wherein the widths of the plurality of deep contacts are different.

13. The semiconductor device of claim 4 , wherein the widths of the plurality of deep contacts are substantially the same.

14. The semiconductor device of claim 4 , further comprising a bottom dielectric layer positioned on the substrate, a middle dielectric layer positioned on the bottom dielectric layer, and a top dielectric layer positioned on the middle dielectric layer;
wherein the plurality of bottom shallow contacts are positioned along the bottom dielectric layer;
wherein the first interconnect layer is positioned along the middle dielectric layer and on the plurality of bottom shallow contacts;
wherein the plurality of top shallow contacts are positioned along the top dielectric layer and on the first interconnect layer.

15. The semiconductor device of claim 14 , further comprising a second interconnect layer positioned on the plurality of top shallow contacts, and a plurality of third interconnect layers positioned on the plurality of deep contacts, wherein the width of the first interconnect layer and a width of the second interconnect layer are different or substantially the same.

16. A semiconductor device, comprising:
a substrate;
a plurality of isolation layers positioned in the substrate;
a word line structure positioned in the substrate and between the plurality of isolation layers;
a plurality of impurity regions positioned in the substrate and adjacent to the word line structure;
a plurality of bottom shallow contacts positioned on the word line structure;
a first interconnect layer positioned on the plurality of bottom shallow contacts;
a plurality of top shallow contacts positioned on the first interconnect layer; and
a plurality of deep contacts positioned on the plurality of impurity regions;
wherein top surfaces of the plurality of top shallow contacts and top surfaces of the plurality of deep contacts are substantially coplanar;
wherein the word line structure extends along a first direction in a top-view perspective;
wherein the plurality of isolation layers extend along the first direction and are parallel to each other.

17. The semiconductor device of claim 16 , widths of the plurality of bottom shallow contacts are less than widths of the plurality of deep contacts, wherein the word line structure comprises:
a word line insulating layer inwardly positioned in the substrate and comprising a U-shaped cross-sectional profile;
a word line conductive layer positioned on the word line insulating layer; and
a word line capping layer positioned on the word line insulating layer and the word line conductive layer;
wherein the plurality of bottom shallow contacts are positioned along the word line capping layer and positioned on the word line conductive layer.

18. The semiconductor device of claim 17 , wherein a width of the word line structure and a width of the first interconnect layer are different.

19. The semiconductor device of claim 17 , further comprising a bottom dielectric layer positioned on the substrate, a middle dielectric layer positioned on the bottom dielectric layer, a top dielectric layer positioned on the middle dielectric layer, a second interconnect layer positioned on the plurality of top shallow contacts, and a plurality of third interconnect layers positioned on the plurality of deep contacts;
wherein the plurality of bottom shallow contacts are positioned along the bottom dielectric layer;
wherein the first interconnect layer is positioned along the middle dielectric layer and on the plurality of bottom shallow contacts;
wherein the plurality of top shallow contacts are positioned along the top dielectric layer and on the first interconnect layer.

20. A method for fabricating a semiconductor device, comprising:
providing a substrate;
forming a word line structure in the substrate and forming a plurality of impurity regions in the substrate and adjacent to the word line structure;
forming a plurality of bottom shallow contacts on the word line structure;
forming a first interconnect layer on the plurality of bottom shallow contacts;
forming a plurality of top shallow contacts on the first interconnect layer; and
forming a plurality of deep contacts on the plurality of impurity regions;
wherein top surfaces of the plurality of top shallow contacts and top surfaces of the plurality of deep contacts are substantially coplanar;
wherein widths of the plurality of bottom shallow contacts are less than widths of the plurality of deep contacts.

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