Array substrate and manufacturing method thereof, and display panel

Abstract

The present disclosure provides an array substrate and a manufacturing method thereof, and a display panel. The array substrate includes an oxide semiconductor layer, a gate insulating layer, a gate electrode, an interlayer insulating layer, and a source-drain electrode metal layer located on a substrate. Wherein the oxide semiconductor layer includes a channel region and conductive regions, the gate insulating layer is respectively overlapped with the conductive regions on both sides of the channel region, and an orthographic projection of a part of the gate electrode corresponding to the oxide semiconductor layer on the substrate falls within a range of an orthographic projection of the channel region on the substrate.

What is claimed is: 
     
       1. An array substrate, comprising:
 a substrate; 
 an oxide semiconductor layer disposed on the substrate, comprising a channel region and conductive regions located at both sides of the channel region; 
 a gate insulating layer disposed on a side of the oxide semiconductor layer away from the substrate; 
 a gate electrode disposed on a side of the gate insulating layer away from the substrate; 
 an interlayer insulating layer disposed on a side of the gate electrode away from the substrate; and 
 a source-drain electrode metal layer disposed on a side of the interlayer insulating layer away from the substrate, and electrically connected to the conductive regions through via holes penetrating the interlayer insulating layer; 
 wherein edges of the gate insulating layer are respectively overlapped with the conductive regions on the both sides of the channel region, and an orthographic projection of a part of the gate electrode corresponding to the oxide semiconductor layer on the substrate falls within a range of an orthographic projection of the channel region on the substrate; and 
 wherein the interlayer insulating layer comprises a first interlayer insulating layer and a second insulating layer, the first interlayer insulating layer is located at a side surface of the second insulating layer close to the substrate, and the gate electrode and the gate insulating layer are exposed from the first interlayer insulating layer. 
 
     
     
       2. The array substrate in  claim 1 , wherein the orthographic projection of the part of the gate electrode corresponding to the oxide semiconductor layer on the substrate coincides with the orthographic projection of the channel region on the substrate. 
     
     
       3. The array substrate in  claim 1 , wherein each of the conductive regions comprises a first conductive region, a second conductive region, and a third conductive region, the second conductive region is located between the first conductive region and the third conductive region, and the second conductive region is in contact with the first conductive region and the third conductive region. 
     
     
       4. The array substrate in  claim 3 , wherein the gate insulating layer is overlapped with the second conductive region and the third conductive region. 
     
     
       5. The array substrate in  claim 1 , wherein a part of the conductive regions not covered by the gate insulating layer is covered by the first interlayer insulating layer, and the source-drain electrode metal layer is electrically connected to the conductive regions through the via holes penetrating the first interlayer insulating layer and the second interlayer insulating layer. 
     
     
       6. The array substrate in  claim 1 , wherein a metal light-shielding layer and a buffer layer are further disposed between the substrate and the oxide semiconductor layer, and the metal light-shielding layer is located at a side of the buffer layer away from the oxide semiconductor layer;
 the source-drain electrode metal layer comprises a source electrode and a drain electrode, wherein the drain electrode is electrically connected to the metal light-shielding layer through a contact hole penetrating the interlayer insulating layer and the buffer layer. 
 
     
     
       7. The array substrate in  claim 1 , wherein the first interlayer insulating layer abuts against a side surface of the gate insulating layer in a direction perpendicular to a thickness direction of the array substrate. 
     
     
       8. A manufacturing method of an array substrate, comprising following steps:
 S 1 , providing a substrate, and manufacturing an oxide semiconductor layer on the substrate; 
 S 2 , manufacturing a gate insulating layer, a gate electrode, and an interlayer insulating layer on the oxide semiconductor layer, and forming a channel region and conductive regions located at both sides of the channel region; 
 S 3 , forming via holes penetrating the interlayer insulating layer and exposing the conductive regions; and 
 S 4 , manufacturing a source-drain electrode metal layer on the interlayer insulating layer, wherein the source-drain electrode metal layer is electrically connected to the conductive regions through the via holes; 
 wherein edges of the gate insulating layer are respectively overlapped with the conductive regions on the both sides of the channel region, and an orthographic projection of a part of the gate electrode corresponding to the oxide semiconductor layer on the substrate falls within a range of an orthographic projection of the channel region on the substrate; and 
 wherein the interlayer insulating layer comprises a first interlayer insulating layer and a second insulating layer, the first interlayer insulating layer is located at a surface of the second insulating layer close to the substrate, and the gate electrode and the gate insulating layer are exposed from the first interlayer insulating layer. 
 
     
     
       9. The manufacturing method of the array substrate in  claim 8 , wherein the S 2  comprises following steps:
 S 21 , manufacturing the gate insulating layer and a gate transition layer stacked on the oxide semiconductor layer, and forming a first conductive region on a part of the oxide semiconductor layer not covered by the gate insulating layer; 
 S 22 , making a first manufacture of the interlayer insulating layer, wherein the interlayer insulating layer covers the first conductive region, at a same time, carriers in the first conductive region diffuse to a part of the oxide semiconductor layer corresponding to the gate insulating layer to form a second conductive region adjacent to the first conductive region; 
 S 23 , etching the gate transition layer to form the gate electrode; and 
 S 24 , making a second manufacture of the interlayer insulating layer to form the interlayer insulating layer covering the gate electrode, the gate insulating layer, and the oxide semiconductor layer, at a same time, the carriers in the first conductive region and the second conductive region diffuse towards a part of the oxide semiconductor layer corresponding to the gate electrode, to form a third conductive region between the part of the oxide semiconductor layer corresponding to the gate electrode and the second conductive region; 
 wherein the first conductive region, the second conductive region, and the third conductive region constitute a conductive region. 
 
     
     
       10. The manufacturing method of the array substrate in  claim 9 , wherein the S 21  comprises following steps:
 S 211 , manufacturing a gate insulating film, a gate metal film, and a photoresist on the oxide semiconductor layer in sequence, the photoresist comprising a reserved area, and a part of the photoresist except the reserved area is removed by a yellow light process; 
 S 212 , etching the gate insulating film and the gate metal film and removing a part of the gate insulating film and the gate metal film except the reserved area corresponding to the gate insulating film and the gate metal film, to form the gate insulating layer and the gate transition layer; and 
 S 213 , making the part of the oxide semiconductor layer not covered by the gate insulating layer conductive to form the first conductive region. 
 
     
     
       11. The manufacturing method of the array substrate in  claim 10 , wherein the S 22  comprises following step:
 making the first manufacture of the interlayer insulating layer on the oxide semiconductor layer and the reserved area of the photoresist to form a first interlayer insulating layer covering the first conductive region, at a same time, the carriers in the first conductive region diffuse to the part of the oxide semiconductor layer corresponding to the gate electrode to form the second conductive region adjacent to the first conductive region and overlapped with the gate insulating layer. 
 
     
     
       12. The manufacturing method of the array substrate in  claim 11 , wherein, after the S 23 , and before the S 24 , the manufacturing method further comprises following step:
 removing the reserved area of the photoresist and a part of the interlayer insulating layer covering the reserved area. 
 
     
     
       13. The manufacturing method of the array substrate in  claim 8 , wherein the part of the oxide semiconductor layer corresponding to the gate electrode constitutes the channel region, and the orthographic projection of the part of the gate electrode corresponding to the oxide semiconductor layer on the substrate coincides with the orthographic projection of the channel region on the substrate. 
     
     
       14. A display panel, comprising an array substrate and an opposed substrate, the array substrate and the opposed substrate disposed opposite to each other, wherein the array substrate comprises:
 a substrate; 
 an oxide semiconductor layer disposed on the substrate, comprising a channel region and conductive regions located at both sides of the channel region; 
 a gate insulating layer disposed on a side of the oxide semiconductor layer away from the substrate; 
 a gate electrode disposed on a side of the gate insulating layer away from the substrate; 
 an interlayer insulating layer disposed on a side of the gate electrode away from the substrate; and 
 a source-drain electrode metal layer disposed on a side of the interlayer insulating layer away from the substrate, and electrically connected to the conductive regions through via holes penetrating the interlayer insulating layer; 
 wherein edges of the gate insulating layer are respectively overlapped with the conductive regions on the both sides of the channel region, and an orthographic projection of a part of the gate electrode corresponding to the oxide semiconductor layer on the substrate falls within a range of an orthographic projection of the channel region on the substrate; and 
 wherein the interlayer insulating layer comprises a first interlayer insulating layer and a second insulating layer, the first interlayer insulating layer is located at a surface of the second insulating layer close to the substrate, and the gate electrode and the gate insulating layer are exposed from the first interlayer insulating layer. 
 
     
     
       15. The display panel in  claim 14 , wherein the orthographic projection of the part of the gate electrode corresponding to the oxide semiconductor layer on the substrate coincides with the orthographic projection of the channel region on the substrate. 
     
     
       16. The display panel in  claim 14 , wherein each of the conductive regions comprises a first conductive region, a second conductive region, and a third conductive region, the second conductive region is located between the first conductive region and the third conductive region, and the second conductive region is in contact with the first conductive region and the third conductive region. 
     
     
       17. The display panel in  claim 16 , wherein the gate insulating layer is overlapped with the second conductive region and the third conductive region. 
     
     
       18. The display panel in  claim 14 , wherein a part of the conductive regions not covered by the gate insulating layer is covered by the first interlayer insulating layer, and the source-drain electrode metal layer is electrically connected to the conductive regions through the via holes penetrating the first interlayer insulating layer and the second interlayer insulating layer. 
     
     
       19. The display panel in  claim 14 , wherein a light-shielding metal layer and a buffer layer are further disposed between the substrate and the oxide semiconductor layer, and the metal light-shielding layer is located at a side of the buffer layer away from the oxide semiconductor layer;
 the source-drain electrode metal layer comprises a source electrode and a drain electrode, wherein the drain electrode is electrically connected to the metal light-shielding layer through a contact hole penetrating the interlayer insulating layer and the buffer layer. 
 
     
     
       20. The display panel in  claim 14 , wherein the first interlayer insulating layer abuts against a side surface of the gate insulating layer in a direction perpendicular to a thickness direction of the array substrate.