Circuit and method for timestamp jitter reduction

Abstract

A circuit and corresponding method generate a filtered timestamp. The circuit comprises recursive filter logic. The circuit generates the filtered timestamp from a received timestamp by filtering the received timestamp via the recursive filter logic. The recursive filter logic reduces jitter in the filtered timestamp relative to jitter of the received timestamp. The jitter represents a deviation of the received timestamp from a target (ideal) timestamp. The circuit outputs the filtered timestamp generated. The filtered timestamp is a more accurate representation of the target timestamp, relative to the received timestamp, due to the jitter reduced.

What is claimed is: 
     
       1. A circuit comprising:
 recursive filter logic, the circuit configured to: 
 (i) generate a filtered timestamp from a received timestamp by filtering the received timestamp via the recursive filter logic, the recursive filter logic configured to reduce jitter in the filtered timestamp relative to jitter of the received timestamp, the jitter of the received timestamp representing a deviation of the received timestamp from a target timestamp, and 
 (ii) output the filtered timestamp generated. 
 
     
     
       2. The circuit of  claim 1 , wherein the circuit is further configured to output the filtered timestamp generated to a timestamp consumer and wherein the timestamp consumer is configured to associate an incoming packet, outgoing packet, or combination thereof, with the filtered timestamp generated and output from the circuit. 
     
     
       3. The circuit of  claim 1 , wherein the received timestamp is received on a cycle-by-cycle basis, wherein the circuit is further configured to generate the filtered timestamp in real time, on the cycle-by-cycle basis, and wherein the cycle-by-cycle basis is based on a clock cycle of a clock of the circuit. 
     
     
       4. The circuit of  claim 1 , wherein the filtered timestamp generated and output is a more accurate representation of the target timestamp, relative to the received timestamp, based on the jitter reduced. 
     
     
       5. The circuit of  claim 1 , wherein the jitter of the received timestamp has a maximum value and an average value and wherein the recursive filter logic is further configured to reduce the maximum value of the jitter, average value of the jitter, or a combination thereof, in the filtered timestamp generated. 
     
     
       6. The circuit of  claim 1 , wherein the received timestamp is a synchronized timestamp, generated from an original timestamp by synchronizing the original timestamp across multiple clock domains, and wherein the jitter reduced is dynamic jitter generated from the synchronizing. 
     
     
       7. The circuit of  claim 1 , wherein the received timestamp is a synchronized timestamp, wherein the circuit is a filter circuit coupled to a timestamp (TS) synchronization circuit, and wherein the TS synchronization circuit is configured to generate the synchronized timestamp from an original timestamp by synchronizing the original timestamp across multiple clock domains. 
     
     
       8. The circuit of  claim 1 , wherein the received timestamp is received on a cycle-by-cycle basis, wherein the recursive filter logic is further configured to implement a recursive least-squares (RLS) filter, wherein the RLS filter is configured to generate an estimated timestamp value of the target timestamp on the cycle-by-cycle basis, and wherein the circuit is further configured to generate the filtered timestamp on the cycle-by-cycle basis, based on the estimated timestamp value generated. 
     
     
       9. The circuit of  claim 1 , wherein the recursive filter logic is further configured to implement a recursive least-squares (RLS) filter, wherein the RLS filter is configured to generate an estimated timestamp value of the target timestamp based on the received timestamp, and wherein the circuit is further configured to generate the filtered timestamp based on the estimated timestamp value generated. 
     
     
       10. The circuit of  claim 1 , wherein the recursive filter logic is further configured to implement a recursive least-squares (RLS) filter and wherein the RLS filter is configured to:
 generate a current estimated timestamp value of the target timestamp; and 
 generate a current estimated line slope value of a line slope of a linear function, the linear function representing the target timestamp, the current estimated timestamp value generated based on a previous estimated timestamp value of the target timestamp and a previous estimated line slope value of the line slope of the linear function, 
 the previous estimated timestamp value and previous estimated line slope value generated by the RLS filter prior to generation of the current estimated timestamp value and current estimated line slope value, respectively. 
 
     
     
       11. The circuit of  claim 10 , wherein the previous estimated timestamp value and the previous estimated line slope value are generated by the RLS filter in a previous clock cycle and wherein the previous clock cycle immediately precedes a current clock cycle in which the current estimated timestamp value and current estimated line slope value are generated. 
     
     
       12. The circuit of  claim 10 , wherein the RLS filter is further configured to generate the current estimated timestamp value based on a product of the previous estimated timestamp value and a number of clock cycles that transpired since a last update of the received timestamp. 
     
     
       13. The circuit of  claim 12 , wherein the number of clock cycles is one. 
     
     
       14. The circuit of  claim 1 , wherein the recursive filter logic is further configured to implement a recursive least-squares (RLS) filter and wherein the RLS filter is configured to:
 employ a first filter gain and a second filter gain; 
 generate a current estimated timestamp value of the target timestamp; 
 generate a current estimated line slope value of a line slope of a linear function, the linear function representing the target timestamp; and 
 generate a residual error, the current estimated timestamp value generated based on the first filter gain and the residual error, the current estimated line slope value generated based on the second filter gain and the residual error. 
 
     
     
       15. The circuit of  claim 14 , wherein the recursive filter logic includes filter-step control logic configured to generate a filter step value, wherein the first filter gain and the second filter gain are based on the filter step value, wherein the filter-step control logic is further configured to increment the filter step value on a cycle-by-cycle basis, wherein the filter step value is associated with a threshold value, and wherein, in an event the filter step value reaches the threshold value, the filter-step control logic is further configured to maintain the filter step value at the threshold value. 
     
     
       16. The circuit of  claim 14 , wherein the previous estimated timestamp value and previous estimated line slope value are generated by the RLS filter in a previous clock cycle and wherein the previous clock cycle immediately precedes a current clock cycle in which the current estimated timestamp value and current estimated line slope value are generated. 
     
     
       17. The circuit of  claim 14 , wherein the RLS filter is further configured to generate the residual error based on a current timestamp value of the received timestamp, a previous estimated timestamp value of the target timestamp, and a previous estimated line slope value of a line slope of the linear function, the previous estimated timestamp value and the previous estimated line slope value generated by the RLS filter prior to generation of the current estimated timestamp value and the current estimated line slope value, respectively. 
     
     
       18. The circuit of  claim 14 , wherein the RLS filter is further configured to generate the residual error based on a number of clock cycles that transpired since a last update of the received timestamp. 
     
     
       19. The circuit of  claim 18 , wherein the number of clock cycles is one. 
     
     
       20. The circuit of  claim 1 , wherein the received timestamp is a synchronized timestamp of an original timestamp, wherein the recursive filter logic is further configured to compute a residual error, wherein the circuit further comprises reset logic, and wherein the reset logic is configured to reset the recursive filter logic, automatically, based on the residual error computed. 
     
     
       21. A method comprising:
 generating a filtered timestamp from a received timestamp by filtering the received timestamp via recursive filter logic, the filtering including reducing jitter in the filtered timestamp relative to jitter of the received timestamp via the recursive filter logic, the jitter of the received timestamp representing a deviation from a target timestamp; and 
 outputting the filtered timestamp generated. 
 
     
     
       22. The method of  claim 21 , wherein the outputting includes outputting the filtered timestamp generated to a timestamp consumer, the timestamp consumer associating an incoming packet, outgoing packet, or combination thereof, with the filtered timestamp generated and output. 
     
     
       23. The method of  claim 21 , further comprising receiving the received timestamp on a cycle-by-cycle basis, wherein the generating includes generating the filtered timestamp in real time, on the cycle-by-cycle basis. 
     
     
       24. The method of  claim 21 , wherein the filtered timestamp generated and output is a more accurate representation of the target timestamp, relative to the received timestamp, based on the jitter reduced. 
     
     
       25. The method of  claim 21 , wherein the jitter of the received timestamp has a maximum value and an average value and wherein reducing the jitter includes reducing the maximum value of the jitter, average value of the jitter, or a combination thereof, in the filtered timestamp generated. 
     
     
       26. The method of  claim 21 , wherein the received timestamp is a synchronized timestamp, generated from an original timestamp by synchronizing the original timestamp across multiple clock domains, and wherein the jitter reduced is dynamic jitter generated from the synchronizing. 
     
     
       27. The method of  claim 21 , wherein the received timestamp is a synchronized timestamp generated from an original timestamp by synchronizing the original timestamp across multiple clock domains. 
     
     
       28. The method of  claim 21 , wherein the method further comprises:
 receiving the received timestamp on a cycle-by-cycle basis; 
 generating an estimated timestamp value of the target timestamp on the cycle-by-cycle basis; and 
 generating the filtered timestamp on the cycle-by-cycle basis, based on the estimated timestamp value generated. 
 
     
     
       29. The method of  claim 21 , wherein the method further comprises:
 generating an estimated timestamp value of the target timestamp based on the received timestamp; and 
 generating the filtered timestamp based on the estimated timestamp value generated. 
 
     
     
       30. The method of  claim 21 , wherein the method further comprises:
 generating a current estimated timestamp value of the target timestamp; and 
 generating a current estimated line slope value of a line slope of a linear function, the linear function representing the target timestamp, the current estimated timestamp value generated based on a previous estimated timestamp value of the target timestamp and a previous estimated line slope value of the line slope of the linear function, the previous estimated timestamp value and previous estimated line slope value generated prior to generation of the current estimated timestamp value and current estimated line slope value, respectively. 
 
     
     
       31. The method of  claim 30 , further comprising generating, in a previous clock cycle, the previous estimated timestamp value and the previous estimated line slope value, wherein the previous clock cycle immediately precedes a current clock cycle in which the current estimated timestamp value and current estimated line slope value are generated. 
     
     
       32. The method of  claim 30 , further comprising generating the current estimated timestamp value based on a product of the previous estimated timestamp value and a number of clock cycles that transpired since a last update of the received timestamp. 
     
     
       33. The method of  claim 32 , wherein the number of clock cycles is one. 
     
     
       34. The method of  claim 21 , wherein the method further comprises:
 employing a first filter gain and a second filter gain; 
 generating a current estimated timestamp value of the target timestamp; 
 generating a current estimated line slope value of a line slope of a linear function, the linear function representing the target timestamp; and 
 generating a residual error, the current estimated timestamp value generated based on the first filter gain and the residual error, the current estimated line slope value generated based on the second filter gain and the residual error. 
 
     
     
       35. The method of  claim 34 , further comprising generating a filter step value, wherein the first filter gain and the second filter gain are based on the filter step value generated, wherein generating the filter step value includes incrementing the filter step value on a cycle-by-cycle basis, wherein the filter step value is associated with a threshold value, and wherein, in an event the filter step value reaches the threshold value, generating the filter step value includes maintaining the filter step value at the threshold value. 
     
     
       36. The method of  claim 34 , further comprising generating, in a previous clock cycle, the previous estimated timestamp value and previous estimated line slope value, wherein the previous clock cycle immediately precedes a current clock cycle in which the current estimated timestamp value and current estimated line slope value are generated. 
     
     
       37. The method of  claim 34 , further comprising:
 generating the residual error based on a current timestamp value of the received timestamp; 
 generating a previous estimated timestamp value of the target timestamp; and 
 generating a previous estimated line slope value of a line slope of the linear function, wherein the previous estimated timestamp value and the previous estimated line slope value are generated prior to generation of the current estimated timestamp value and the current estimated line slope value, respectively. 
 
     
     
       38. The method of  claim 37 , further comprising generating the residual error based on a number of clock cycles that transpired since a last update of the received timestamp. 
     
     
       39. The method of  claim 38 , wherein the number of clock cycles is one. 
     
     
       40. The method of  claim 21 , wherein the received timestamp is a synchronized timestamp of an original timestamp and wherein the method further comprises:
 computing a residual error; and 
 resetting the recursive filter logic, automatically, based on the residual error computed. 
 
     
     
       41. An apparatus comprising:
 means for generating a filtered timestamp from a received timestamp by filtering the received timestamp, the filtering including reducing jitter in the filtered timestamp relative to jitter of the received timestamp via recursive filter logic, the jitter of the received timestamp representing a deviation from a target timestamp; and 
 means for outputting the filtered timestamp generated. 
 
     
     
       42. The circuit of  claim 1 , further comprising:
 input format-conversion logic configured to convert the received timestamp from an original timestamp format to an intermediate timestamp format; and 
 output format-conversion logic configured to convert the filtered timestamp from the intermediate timestamp format to the original timestamp format and output the filtered timestamp in the original timestamp format, wherein the original timestamp format is based on seconds and nanoseconds and wherein the intermediate timestamp format is based on seconds and fractional seconds. 
 
     
     
       43. The circuit of  claim 1 , wherein the recursive filter logic is further configured to:
 implement a recursive least-squares (RLS) filter; and 
 apply the RLS filter to a portion of the received timestamp, wherein the portion is a least significant bit (LSB) portion of the received timestamp and wherein the LSB portion is of lesser significance relative to a most significant bit (MSB) portion of the received timestamp. 
 
     
     
       44. The circuit of  claim 14 , wherein respective values of the first filter gain and second filter gain are rounded to a nearest power-of-two. 
     
     
       45. The circuit of  claim 15 , wherein the threshold value is sixteen.