Apparatus and method for sharing data between a host and a memory system based on data characteristics

Abstract

A memory system includes a memory device and a controller. The memory device includes a plurality of memory cells. The controller is configured to select first map data entries associated with first data entries stored in a first region of the memory device that includes some of the plurality of memory cells, to exclude a second map data entry associated with second data entry sequentially read from among the first map data entries, and to transmit a remaining first map data entry to an external device.

What is claimed is: 
     
       1. A memory system, comprising:
 a memory device including a plurality of memory cells; and 
 a controller configured to: 
 identify first map data associated with first data stored in a first region of the memory device that includes some of the plurality of memory cells; 
 determine second map data among the first map data, the second map data associated with second data, which is sequentially readable data among the first data; and 
 transmit map data, excluding the second map data from the first map data, to an external device. 
 
     
     
       2. The memory system according to  claim 1 , wherein the controller is further configured to add a third region into the first region, and to transmit third map data, which is associated with third data stored in the third region, to the external device. 
     
     
       3. The memory system according to  claim 1 , wherein a logical address range regarding map data transmitted by the controller is determined based on a file system used by the external device. 
     
     
       4. The memory system according to  claim 1 , wherein the controller is configured to, in response to a request input from the external device, migrate some of the first data in the first region to a contiguously allocated location in another region. 
     
     
       5. The memory system according to  claim 4 , wherein the controller is configured to invalidate previously transmitted map data associated with the some of the first data migrated to the contiguously allocated location. 
     
     
       6. The memory system according to  claim 1 , wherein the controller is further configured to determine a first logical address range based on an access pattern regarding the memory device in an idle state when there is no request input from the external device, to establish a contiguously allocated location corresponding to memory cells storing data associated with the first logical address range, and to migrate the data to the contiguously allocated location in the memory device. 
     
     
       7. The memory system according to  claim 6 , wherein the controller is further configured to sort the data associated with the first logical address range for sequential read operations during garbage collection while performing a garbage collection operation for the memory device. 
     
     
       8. The memory system according to  claim 7 , wherein the controller is further configured to transmit, to the external device, a notice indicating that previously transmitted map data associated with the first logical address range become invalid, after sorting the data for the sequential read operation. 
     
     
       9. The memory system according to  claim 1 , wherein the controller is configured to determine the first region based on a size of the map data transmitted to the external device. 
     
     
       10. A method for operating a memory system including a memory device, the memory device including memory blocks including a plurality of memory cells, the method comprising:
 identifying first map data associated with first data stored in a host performance booster (HPB) region including some of the plurality of memory cells; 
 determining second map data among the first map data, the second map data associated with second data which is sequentially readable data among the first data stored in the HPB region; and 
 transmitting map data, excluding the second map data from the first map data, to a host. 
 
     
     
       11. The method according to  claim 10 , further comprising:
 performing a file-based optimization (FBO) operation for at least some of the HPB region in the memory device; and 
 invalidating some of the first map data corresponding to the at least some of the HPB region. 
 
     
     
       12. The method according to  claim 10 , further comprising:
 adding a region irrelevant to a file-based optimization (FBO) operation to the HPB region; and 
 transmitting at least one map data corresponding to an added region to the host. 
 
     
     
       13. The method according to  claim 10 , wherein a file-based optimization (FBO) operation is performed for a first logical address range determined based on a file system used by the host. 
     
     
       14. The method according to  claim 13 , wherein the performing the FBO operation comprises:
 establishing, in response to a request input from the host, a file-based optimization (FBO) region including memory cells contiguously allocated for storing data associated with the first logical address range; and 
 migrating the data associated with the first logical address range to the FBO region. 
 
     
     
       15. The method according to  claim 13 , wherein the performing the FBO operation comprises:
 determining the first logical address range based on an access regarding the memory device in an idle state when there is no request input from the host; 
 establishing a file-based optimization (FBO) region including memory cells contiguously allocated for storing data associated with the first logical address range; and 
 migrating the data associated with the first logical address range to the FBO region. 
 
     
     
       16. The method according to  claim 13 , further comprising:
 checking a blank region capable of storing data associated with the first logical address range. 
 
     
     
       17. The method according to  claim 11 , further comprising:
 performing the FBO operation along with garbage collection for the memory device. 
 
     
     
       18. A controller coupled to a memory including a plurality of regions, each region including a plurality of memory cells, the controller including at least one processor, at least one memory, and logic in which at least a portion of the logic is comprised in hardware and executed by the at least one processor to:
 program data input from an external device in a first region among the plurality of regions; 
 migrate the data from the first region to either a second region or a third region from among the plurality of regions based on an attribute of the data, the second region allocated for a random read operation, the third region allocated for a sequential read operation; 
 transmitting map data associated with the data stored in the second region, not the third region, to the external device; 
 performing the random read operation for the data stored in the second region, in response to a first read request along with an address of the second region, which is input from the external device; and 
 performing the sequential read operation for the data stored in the third region, in response to a second read request input from the external device. 
 
     
     
       19. The controller according to  claim 18 , wherein the first region includes a single-level cell (SLC) buffer, while the second region and the third region individually include a multi-level cell (MLC) block. 
     
     
       20. The controller according to  claim 18 , wherein the logic is configured to perform data migration for data from the first region to the third region, and the data are determined based on a file system used by the external device.