Layout pattern for static random access memory

Abstract

The invention provides a layout pattern cell of a static random access memory (SRAM), which at least comprises a first SRAM cell, a plurality of gate structures spanning a plurality of fin structures, so as to form a first pull-up transistor, a second pull-up transistor, a first pull-down transistor, a second pull-down transistor, a first access transistor, a second access transistor, a third access transistor, a fourth access transistor, a first parasitic transistor and a second parasitic transistor located on a substrate, the first parasitic transistor and the first pull-down transistor span the same fin structure, and the fin structure spanned by the first parasitic transistor and the first pull-down transistor is a continuous structure.

What is claimed is: 
     
       1. A layout pattern unit of a static random access memory (SRAM), at least comprising:
 a first region comprises a first SRAM cell, which includes:
 a plurality of fin structures located on a substrate; 
 a plurality of gate structures located on the substrate, wherein the gate structures span the plurality of fin structures to form a PU 1  (first pull-up transistor), a PU 2  (second pull-up transistor), a PD 1  (first pull-down transistor), a PD 2  (second pull-down transistor), a PG 1 A (first access transistor), a PG 1 B (second access transistor), a PG 2 A (third access transistor), a PG 2 B (fourth access transistor), a first parasitic transistor and a second parasitic transistor located on the substrate; 
 wherein the first parasitic transistor and the PD 1  span the same fin structure, and the fin structure spanned by the first parasitic transistor and the PD 1  is a continuous structure. 
 
 
     
     
       2. The layout pattern unit of the SRAM according to  claim 1 , wherein a source and a gate of the first parasitic transistor are connected to each other, and further connected to a source of the PD 1 . 
     
     
       3. The layout pattern unit of the SRAM according to  claim 2 , wherein the source and the gate of the first parasitic transistor and the source of the PD 1  are further connected to a Vss voltage source. 
     
     
       4. The layout pattern unit of SRAM according to  claim 1 , wherein the gate structures comprise a first gate structure, a second gate structure, a third gate structure and a fourth gate structure, wherein the PD 1  comprises the first gate structure, the PG 1 B comprises the second gate structure, the PG 1 A comprises the third gate structure and the first parasitic transistor comprises the fourth gate structure. 
     
     
       5. The layout pattern unit of the SRAM according to  claim 4 , further comprising:
 a first metal layer electrically connected to a source of the PD 1 ; 
 a second metal layer electrically connected to a source of the PG 1 B; 
 a third metal layer electrically connected to a source of the PG 1 A; and 
 a fourth metal layer electrically connected to a source of the first parasitic transistor. 
 
     
     
       6. The layout pattern unit of SRAM according to  claim 5 , wherein the distance between the first metal layer and the second metal layer in a horizontal direction is equal to the distance between the third metal layer and the fourth metal layer in the horizontal direction. 
     
     
       7. The layout pattern unit of SRAM according to  claim 5 , wherein the distance from the second metal layer to the fin structure spanned by the first parasitic transistor and the PD 1  in a horizontal direction is equal to the distance from the third metal layer to the fin structure spanned by the first parasitic transistor and the PD 1  in the horizontal direction. 
     
     
       8. The layout pattern unit of SRAM according to  claim 5 , wherein the second metal layer and the third metal layer are equal in area and size. 
     
     
       9. The layout pattern unit of SRAM according to  claim 6 , wherein the first metal layer and the fourth metal layer are aligned in a vertical direction, and the second metal layer and the third metal layer are aligned in the vertical direction. 
     
     
       10. The layout pattern unit of SRAM according to  claim 5 , wherein the first metal layer is electrically connected to a Vss voltage source, the second metal layer is electrically connected to a bit line, the third metal layer is electrically connected to another bit line, and the fourth metal layer is electrically connected to the Vss voltage source. 
     
     
       11. The layout pattern unit of the SRAM according to  claim 5 , further comprising a fifth metal layer, which is connected and directly contacted with the fourth metal layer and the fourth gate structure and arranged along a vertical direction. 
     
     
       12. The layout pattern unit of the SRAM according to  claim 11 , further comprising a second region adjacent to the first region, and another SRAM cell is comprised in the second region, wherein the SRAM cell in the second region and the SRAM cell comprised in the first region are arranged in mirror images. 
     
     
       13. The layout pattern unit of the SRAM according to  claim 12 , wherein the fifth metal layer is further connected to a parasitic transistor in the second region. 
     
     
       14. The layout pattern unit of the SRAM according to  claim 12 , wherein the fin structure spanned by the first parasitic transistor and the PD 1  extends into the second region and is a continuous structure. 
     
     
       15. The layout pattern unit of the SRAM according to  claim 12 , wherein the PU 1  spans one of the fin structures, and the fin structure spanned by the PU 1  does not extend to the second region. 
     
     
       16. The layout pattern unit of the SRAM according to  claim 12 , wherein the substrate further comprises a plurality of regions, and each of the plurality of regions comprises an SRAM cell, wherein the first region, the second region and the plurality of regions are arranged in the same direction, and the fin structure spanned by the first parasitic transistor and the PD 1  extends into the first region, the second region and the plurality of regions without being cut off. 
     
     
       17. The layout pattern unit of the SRAM according to  claim 16 , further comprising an active region under the fin structure spanned by the first parasitic transistor and the PD 1 , and the active region extends into the first region, the second region and the plurality of regions without being cut off. 
     
     
       18. The layout pattern unit of the SRAM according to  claim 1 , wherein the PU 1 , the PD 1  and the PG 1 B are aligned along a horizontal direction when viewed from a top view, and the PG 1 A and the first parasitic transistor are aligned along the horizontal direction. 
     
     
       19. The layout pattern unit of the SRAM according to  claim 18 , wherein the PD 1  and the first parasitic transistor are aligned along a vertical direction when viewed from the top view, and the vertical direction and the horizontal direction are perpendicular to each other. 
     
     
       20. The layout pattern unit of the SRAM according to  claim 1 , wherein the numbers of the fin structures spanned by the first parasitic transistor and the spanned by the PD 1  are equal.