Package structure

Abstract

A package structure is provided herein, which includes a substrate, an integrated transistor, and an encapsulation structure. The integrated transistor is disposed on the substrate and includes a transistor, a capacitor, a resistor, a first Zener diode, and a second Zener diode. The transistor includes a gate, a drain, and a source. The capacitor is electrically connected to the gate, and the resistor is electrically connected to the gate. The first Zener diode includes a first anode and a first cathode electrically connected to the gate. The second Zener diode includes a second anode electrically connected to the first anode and a second cathode electrically connected to the source. The encapsulation structure encapsulates the integrated transistor. The package structure includes a gate terminal, a drain terminal, and a source terminal.

What is claimed is: 
     
       1. A package structure, comprising:
 a substrate; 
 a first carrier, a second carrier, and a third carrier, each disposed on the substrate 
 an integrated transistor, disposed on the substrate, wherein the integrated transistor comprises:
 a transistor, comprising a gate, a drain, and a source, wherein the drain is electrically connected to the second carrier, and the gate is electrically connected to the third carrier; 
 a capacitor, electrically connected to the gate; 
 a resistor, electrically connected to the gate; 
 a first Zener diode, comprising a first anode and a first cathode, wherein the first cathode is electrically connected to the gate; and 
 a second Zener diode, comprising a second anode and a second cathode, wherein the second anode is electrically connected to the first anode, and the second cathode is electrically connected to the source through the first carrier; and 
 
 an encapsulation structure, encapsulating the integrated transistor; 
 wherein the package structure comprises a gate terminal, a drain terminal, and a source terminal. 
 
     
     
       2. The package structure of  claim 1 , wherein the transistor is an enhancement-mode high electron mobility transistor. 
     
     
       3. The package structure of  claim 1 , further comprising:
 a fourth carrier, disposed on the substrate, wherein the gate is electrically connected to the first cathode through the fourth carrier, and the capacitor and the resistor are electrically connected between the third carrier and the fourth carrier respectively. 
 
     
     
       4. The package structure of  claim 3 , wherein the transistor and the second Zener diode are disposed on the first carrier, the first Zener diode is disposed on the fourth carrier, and the capacitor and the resistor are disposed between the third carrier and the fourth carrier. 
     
     
       5. The package structure of  claim 4 , wherein each of the first carrier, the second carrier, the third carrier, and the fourth carrier is a conductive carrier, wherein the gate is adjacent to the fourth carrier, and electrically connected to the fourth carrier through a first bonding wire, wherein the first Zener diode is electrically connected to the second Zener diode through a second bonding wire, and the capacitor and the resistor are connected between the third carrier and the fourth carrier respectively. 
     
     
       6. The package structure of  claim 1 , further comprising:
 a first bottom plate, disposed below the substrate and the first carrier; 
 a second bottom plate, disposed below the substrate and the second carrier; 
 a third bottom plate, disposed below the substrate and the third carrier; 
 a fourth bottom plate, disposed below the substrate, the first carrier, and the transistor; and 
 a plurality of connecting elements; 
 wherein the first bottom plate, the second bottom plate, and the third bottom plate are electrically connected to the first carrier, the second carrier, and the third carrier through three of the plurality of connecting elements respectively. 
 
     
     
       7. The package structure of  claim 6 , wherein the source terminal comprises the first bottom plate, the drain terminal comprises the second bottom plate, and the gate terminal comprises the third bottom plate. 
     
     
       8. The package structure of  claim 6 , wherein the first carrier is connected to the fourth bottom plate through another one of the plurality of connecting elements. 
     
     
       9. The package structure of  claim 8 , wherein the substrate comprises a plurality of through-holes through the substrate, and the plurality of connecting elements are formed in the through-holes respectively. 
     
     
       10. The package structure of  claim 6 , wherein the substrate comprises a plurality of side surfaces, and the connecting elements are formed on the side surfaces. 
     
     
       11. The package structure of  claim 10 , further comprising:
 a fifth carrier, disposed on the substrate, wherein the fifth carrier and the first carrier are separated from each other and disposed on the substrate; and 
 a fifth bottom plate, disposed below the substrate and the fifth carrier; 
 wherein the fifth carrier is electrically connected to the fifth bottom plate through another one of the plurality of connecting elements. 
 
     
     
       12. The package structure of  claim 3 , wherein the third carrier comprises a gap and/or the fourth carrier comprises a gap. 
     
     
       13. The package structure of  claim 12 , wherein the gap of the third carrier is T-shaped and/or the gap of the fourth carrier is T-shaped. 
     
     
       14. The package structure of  claim 1 , further comprising:
 an insulating plate, disposed on the substrate; 
 a sixth carrier, disposed on the insulating plate; and 
 a seventh carrier, disposed on the insulating plate, wherein the sixth carrier is electrically connected to the gate terminal; 
 wherein the source and the second cathode are electrically connected to the substrate, and the capacitor and the resistor are electrically connected to the sixth carrier and the seventh carrier. 
 
     
     
       15. The package structure of  claim 14 , wherein the first Zener diode is disposed on the sixth carrier, and the capacitor and the resistor are disposed between the sixth carrier and the seventh carrier. 
     
     
       16. The package structure of  claim 15 , wherein the gate of the transistor is adjacent to the sixth carrier, and the gate is connected to the sixth carrier through a bonding wire.