Detecting power line carrier presence in a branch circuit and improving AF detection and nuisance tripping in CAFI/DF breaker

Abstract

A method and system are provided to detect the presence of an arc fault signal on a circuit of a power distribution system. The method and system can involve: sampling a signal measuring electrical activity on the circuit, the sampled signal corresponding to a signal strength of the electrical activity on the circuit, the sampled signal comprising a plurality of sample segments; for each sample segment, computing segment properties including a signal-to-noise ratio and a root-mean-square; generating a pattern representing a presence of any signal transition over a signal sample period for the sampled signal according to the computed segment properties for each sample segment of the sampled signal; and determining a presence of an arc fault signal based on the generated pattern and predetermined pattern(s) of PLC activity on the circuit.

The invention claimed is: 
     
       1. A method comprising:
 sampling, by a controller, a signal measuring electrical activity on a circuit of a power distribution system, the sampled signal corresponding to a signal strength of the electrical activity on the circuit, the sampled signal comprising a plurality of sample segments; 
 for each sample segment, computing segment properties including a signal-to-noise ratio (SNR) and a root-mean-square (RMS); 
 generating, by the controller, a pattern representing a presence of any signal transition over a signal sample period for the sampled signal according to the computed segment properties for each sample segment of the sampled signal; and 
 determining, by the controller, a presence of an arc fault signal based on the generated pattern and one or more predetermined patterns of power line carrier (PLC) activity on the circuit. 
 
     
     
       2. The method of  claim 1 , further comprising:
 determining, by the controller, a presence of PLC activity across the circuit; 
 wherein the segment properties are computed in response to at least the presence of PLC activity on the circuit. 
 
     
     
       3. The method of  claim 1 , wherein the generated pattern is a binary word having side regions reflecting potential side transitions and a center region reflecting potential center transitions, the presence of an arc fault signal is determined when the side transitions of the generated pattern have a non-zero value and diminish to a zero value in the center transitions of the generated pattern, the side transitions with the non-zero value representing captured transitions around zero-cross around arc strike and quench regions, the center transitions with the zero value representing PLC communication. 
     
     
       4. The method of  claim 1 , wherein the generating operation comprises:
 assigning one of a positive, negative or zero value based on the computed SNR and/or RMS for each of the sample segments in comparison to a respective segment property threshold; 
 creating a first binary word to reflect any positive vector representations across the plurality of sample segments; 
 creating a second binary word to reflect any negative vector representation across the plurality of sample segments; and 
 applying a XNOR (Exclusive Not Or) function to the first and second binary words to create a third binary word for the sampled signal. 
 
     
     
       5. The method of  claim 4 , wherein the determining comprises:
 analyzing a value of side transitions/regions and center transitions/region from the third binary word to detect a presence of an arc fault signal. 
 
     
     
       6. The method of  claim 4 , wherein the segment property threshold can comprise a dynamic threshold. 
     
     
       7. The method of  claim 1 , further comprising:
 determining one or more patterns of PLC activity on the circuit, the one or more patterns of PLC activity including at least a pattern of PLC beacon; and 
 storing the one or more patterns of PLC activity as the one or more predetermined patterns of PLC activity. 
 
     
     
       8. The method of  claim 1 , further comprising:
 in response to a detection of an absence of PLC activity, performing fault detection by comparing a signal strength of high frequency signals within an electrical activity, including voltage or current, to a set of dynamic thresholds. 
 
     
     
       9. The method of  claim 1 , wherein the PLC activity can comprise a PLC beacon or PLC communication. 
     
     
       10. The method of  claim 1 , wherein the sampled signal comprises an RSSI (Receiver Signal Strength Indicator) signal, which is generated by a logarithmic amplifier device based on electrical signals monitored on the circuit by at least one sensor, each of the sample segments of the sampled signal having the same length which comprises a half-cycle signal. 
     
     
       11. A system comprising:
 a memory; and 
 a processor configured to:
 sample a signal measuring electrical activity on a circuit of a power distribution system, the sampled signal corresponding to a signal strength of the electrical activity on the circuit, the sampled signal comprising a plurality of sample segments; 
 for each sample segment, compute segment properties including a signal-to-noise ratio (SNR) and a root-mean-square (RMS); 
 generate a pattern representing a presence of any signal transition over a signal sample period for the sampled signal according to the computed segment properties for each sample segment of the sampled signal; and 
 determine a presence of an arc fault signal based on the generated pattern and one or more predetermined patterns of power line carrier (PLC) activity on the circuit. 
 
 
     
     
       12. The system of  claim 11 , wherein the processor is further configured to:
 determine a presence of PLC activity across the circuit; 
 wherein the segment properties are computed in response to at least the presence of PLC activity on the circuit. 
 
     
     
       13. The system of  claim 11 , wherein the generated pattern is a binary word having side regions reflecting potential side transitions and a center region reflecting potential center transitions, the presence of an arc fault signal is determined when the side transitions of the generated pattern have a non-zero value and diminish to a zero value in the center transitions of the generated pattern, the side transitions with the non-zero value representing captured transitions around zero-cross around arc strike and quench regions, the center transitions with the zero value representing PLC communication. 
     
     
       14. The system of  claim 11 , wherein, to generate the pattern, the processor is configured to:
 assign one of a positive, negative or zero value based on the computed SNR and/or RMS for each of the sample segments in comparison to a respective segment property threshold; 
 create a first binary word to reflect any positive vector representations across the plurality of sample segments; 
 create a second binary word to reflect any negative vector representation across the plurality of sample segments; and 
 apply a XNOR (Exclusive Not Or) function to the first and second binary words to create a third binary word for the sampled signal. 
 
     
     
       15. The system of  claim 14 , wherein, to determine the presence of an arc fault signal, the processor is configured to:
 analyze a value of side transitions/regions and center transitions/region from the third binary word to detect a presence of an arc fault signal. 
 
     
     
       16. The system of  claim 14 , wherein the segment property threshold can comprise a dynamic threshold. 
     
     
       17. The system of  claim 11 , wherein the processor is further configured to:
 determine one or more patterns of PLC activity on the circuit, the one or more patterns of PLC activity including at least a pattern of PLC beacon; and 
 store in memory the one or more patterns of PLC activity as the one or more predetermined patterns of PLC activity. 
 
     
     
       18. The system of  claim 11 , wherein the processor is further configured to:
 in response to a detection of an absence of PLC activity, perform fault detection by comparing a signal strength of high frequency signals within an electrical activity, including voltage or current, to a set of dynamic thresholds. 
 
     
     
       19. The system of  claim 11 , wherein the PLC activity can comprise a PLC beacon or PLC communication. 
     
     
       20. The system of  claim 11 , wherein the sampled signal comprises an RSSI (Receiver Signal Strength Indicator) signal, which is generated by a logarithmic amplifier device based on electrical signals monitored on the circuit by at least one sensor, each of the sample segments of the sampled signal having the same length which comprises a half-cycle signal. 
     
     
       21. A non-transitory computer medium storing computer executable code, which when executed by one or more processors, is configured to implement a method comprising:
 sampling, by a controller, a signal measuring electrical activity on a circuit of a power distribution system, the sampled signal corresponding to a signal strength of the electrical activity on the circuit, the sampled signal comprising a plurality of sample segments; 
 for each sample segment, computing segment properties including a signal-to-noise ratio (SNR) and a root-mean-square (RMS); 
 generating, by the controller, a pattern representing a presence of any signal transition over a signal sample period for the sampled signal according to the computed segment properties for each sample segment of the sampled signal; and 
 determining, by the controller, a presence of an arc fault signal based on the generated pattern and one or more predetermined patterns of power line carrier (PLC) activity on the circuit.