Power distribution architecture with series-connected bus converter

Abstract

Apparatus for power conversion are provided. One apparatus includes a power converter including an input circuit and an output circuit. The power converter is configured to receive power from a source for providing power at a DC source voltage V S . The power converter is adapted to convert power from the input circuit to the output circuit at a substantially fixed voltage transformation ratio K DC =V OUT /V IN at an output current, wherein V IN is an input voltage and V OUT is an output voltage. The input circuit and at least a portion of the output circuit are connected in series across the source, such that an absolute value of the input voltage V IN applied to the input circuit is approximately equal to the absolute value of the DC source voltage V S minus a number N times the absolute value of the output voltage V OUT , where N is at least 1.

What is claimed is: 
     
       1. An apparatus, comprising:
 a bus converter circuit having a first terminal, a second terminal, and a common terminal and being configured to convert power in a direction, the direction being one of the following:
 (a) a first direction in which the first terminal and common terminal form an input for receiving input power at a first voltage, V1, and the second terminal and the common terminal form an output for delivering output power at a second voltage, V2, or 
 (b) a second direction in which the second terminal and the common terminal form an input for receiving input power at the second voltage, V2, and the first terminal and the common terminal form an output for delivering output power at the first voltage, V1; 
 
 wherein the input and output are galvanically connected; 
 wherein over a range of input voltages the bus converter circuit uses an essentially fixed voltage transformation ratio, K, equal to the second voltage, V2 divided by the first voltage, V1, (K=V2/V1), to convert power in the direction, such that output power delivered in the first direction is at the second voltage, V2=K×V1, and output power delivered in the second direction is at the first voltage, V1=V2/K; 
 wherein the first voltage, V1, is greater than the second voltage, V2; 
 wherein the bus converter circuit includes (i) a transformer having a first winding and a second winding, (ii) a plurality of switches, and (iii) a controller configured to operate the plurality of switches in a series of converter operating cycles; 
 wherein each converter operating cycle includes a first and a second power transfer interval, the first and second power transfer intervals having essentially equal durations, and wherein during the first power transfer interval a first set of the plurality of switches is ON and power is converted in the direction, and during the second power transfer interval a second set of the plurality of switches is ON and power is converted in the direction; 
 wherein the bus converter circuit is configured during the first power transfer interval (a) to form a first series circuit in which at least the following elements are all connected in series without regard to order: at least one of the first or second terminals, at least one of the first or second windings of the transformer, at least one of the plurality of switches in the first set, and at least one capacitor, and (b) to conduct current in the direction between the first terminal and the second terminal; 
 wherein the bus converter circuit is configured during the second power transfer interval (a) to form a second series circuit in which at least the following elements are all connected in series without regard to order: at least one of the first or second terminals, at least one of the first or second windings of the transformer, at least one of the plurality of switches in the second set, and at least one capacitor, and (b) to conduct current in the direction between the first terminal and the second terminal; 
 wherein the bus converter circuit is configured to, before the first power transfer interval, reduce a voltage across a first ZVS switch prior to turning the first ZVS switch ON, such that the voltage across the first ZVS switch is reduced when the first ZVS switch is turned ON, the first ZVS switch being at least one of the plurality of switches in the first set; and 
 wherein the bus converter circuit is configured to, before the second power transfer interval, reduce a voltage across a second ZVS switch prior to turning the second ZVS switch ON, such that the voltage across the second ZVS switch is reduced when the second ZVS switch is turned ON, the second ZVS switch being at least one of the plurality of switches in the second set. 
 
     
     
       2. The apparatus of  claims 1 , wherein the bus converter circuit is a self-contained assembly adapted to be installed as a unit. 
     
     
       3. A computer apparatus, comprising:
 a power distribution system including an input bus for receiving power at a relatively high safe voltage, preferably approximately 48 Volts; 
 one or more bus converter circuits of  claim 1 , connected to receive power from the input bus; 
 one or more power busses connected to receive power from the one or more bus converter circuits; 
 a plurality of regulators, each having an input connected to receive power from the one or more power busses and an output for delivering a regulated output; and 
 one or more semiconductor processors connected to receive power from one or more of the plurality of regulators. 
 
     
     
       4. The apparatus of  claim 1 , wherein forming the first and second series circuits comprises at least two of the first and second terminals. 
     
     
       5. The apparatus of  claim 4 , further comprising:
 a power distribution bus connected to distribute power from the output; and 
 a plurality of voltage regulators, wherein each voltage regulator comprises a regulator input connected to the power distribution bus to receive power from the output and a regulator output connected to supply power to a respective load, the plurality of voltage regulators each being separated by a distance from the bus converter circuit. 
 
     
     
       6. The apparatus of  claim 5 , wherein the direction is the first direction. 
     
     
       7. The apparatus of  claim 6 , wherein the respective load comprises a computer processor. 
     
     
       8. A computer apparatus, comprising:
 a power distribution system including an input bus for receiving power at a relatively high safe voltage, preferably approximately 48 Volts; 
 one or more bus converter circuits of  claim 4 , connected to receive power from the input bus; 
 one or more power busses connected to receive power from the one or more bus converter circuits; 
 a plurality of regulators, each having an input connected to receive power from the one or more power busses and an output for delivering a regulated output; and 
 one or more semiconductor processors connected to receive power from one or more of the plurality of regulators. 
 
     
     
       9. The apparatus of  claim 4 , wherein the bus converter circuit is further capable of converting power in either of the first direction or the second direction and the direction is a function of conditions external to the bus converter circuit. 
     
     
       10. A computer apparatus, comprising:
 a power distribution system including an input bus for receiving power at a relatively high safe voltage, preferably approximately 48 Volts; 
 one or more bus converter circuits of  claim 9 , connected to receive power from the input bus; 
 one or more power busses connected to receive power from the one or more bus converter circuits; 
 a plurality of regulators, each having an input connected to receive power from the one or more power busses and an output for delivering a regulated output; and 
 one or more semiconductor processors connected to receive power from one or more of the plurality of regulators. 
 
     
     
       11. The apparatus of  claim 4 , wherein the first series circuit comprises one or more of the following: (a) at least one component that is not in the second series circuit, (b) at least one component that is in the second series circuit but is connected in an order that is different from in the second series circuit, or (c) at least one component that is in the second series circuit but is connected to carry a current that flows in a direction that is opposite from a current that the component carries in the second series circuit. 
     
     
       12. A computer apparatus, comprising:
 a power distribution system including an input bus for receiving power at a relatively high safe voltage, preferably approximately 48 Volts; 
 one or more bus converter circuits of  claim 11 , connected to receive power from the input bus; 
 one or more power busses connected to receive power from the one or more bus converter circuits; 
 a plurality of regulators, each having an input connected to receive power from the one or more power busses and an output for delivering a regulated output; and 
 one or more semiconductor processors connected to receive power from one or more of the plurality of regulators. 
 
     
     
       13. The apparatus of  claim 4 , wherein the first set of switches includes one or more switches that are not in the second set of switches. 
     
     
       14. The apparatus of  claim 4 , wherein the first set of switches does not include any switches that are in the second set of switches. 
     
     
       15. The apparatus of  claim 4 , wherein at least one winding of the first series circuit is different than at least one winding of the second series circuit. 
     
     
       16. The apparatus of  claim 4 , wherein at least one winding of the first series circuit is the same as at least one winding of the second series circuit. 
     
     
       17. The apparatus of  claim 16 , wherein the at least one winding is configured in the first series circuit to carry current in one direction and in the second series circuit to carry current in another direction opposite to the one direction. 
     
     
       18. The apparatus of  claim 16 , wherein the first series circuit and the second series circuit each comprises at least two windings of the transformer. 
     
     
       19. The apparatus of  claims 18 , wherein the bus converter circuit is a self-contained assembly adapted to be installed as a unit. 
     
     
       20. A computer apparatus, comprising:
 a power distribution system including an input bus for receiving power at a relatively high safe voltage, preferably approximately 48 Volts; 
 one or more bus converter circuits of  claim 18 , connected to receive power from the input bus; 
 one or more power busses connected to receive power from the one or more bus converter circuits; 
 a plurality of regulators, each having an input connected to receive power from the one or more power busses and an output for delivering a regulated output; and 
 one or more semiconductor processors connected to receive power from one or more of the plurality of regulators. 
 
     
     
       21. The apparatus of  claim 18 , wherein the at least two windings in the first and second series circuits each comprises the first winding and the second winding, and the first winding and the second winding are configured in the first series circuit to carry current in one direction and are configured in the second series circuit to carry current in another direction opposite to the one direction. 
     
     
       22. The apparatus of  claim 21 , wherein the first and second windings are configured in a first order in the first series circuit and in a second different order in the second series circuit. 
     
     
       23. The apparatus of  claim 22 , wherein the first and second windings are configured in the first series circuit for current to flow in the first direction and in the second series circuit for current to flow in the another direction. 
     
     
       24. The apparatus of  claim 18 , wherein the first and second series circuits form a first and a second series resonant circuit, each having a characteristic resonant period; and the essentially equal duration of the first and second power transfer intervals is less than each characteristic resonant period. 
     
     
       25. The apparatus of  claims 24 , wherein the bus converter circuit is a self-contained assembly adapted to be installed as a unit. 
     
     
       26. The apparatus of  claim 18 , wherein the transformer comprises a third winding and the first and second series circuits each further comprises the third winding. 
     
     
       27. The apparatus of  claim 26 , wherein the first, second, and third windings are configured in the first series circuit to carry current in one direction and in the second series circuit to carry current in another direction opposite to the one direction. 
     
     
       28. The apparatus of  claim 26 , wherein the first set of switches includes one or more switches that are not in the second set of switches. 
     
     
       29. The apparatus of  claim 26 , wherein the first set of switches does not include any switches that are in the second set of switches. 
     
     
       30. The apparatus of  claim 16 , wherein the transformer comprises a third winding and the first series circuit and the second series circuit each comprises at least two windings of the transformer. 
     
     
       31. The apparatus of  claims 30 , wherein the bus converter circuit is a self-contained assembly adapted to be installed as a unit. 
     
     
       32. A computer apparatus, comprising:
 a power distribution system including an input bus for receiving power at a relatively high safe voltage, preferably approximately 48 Volts; 
 one or more bus converter circuits of  claim 30 , connected to receive power from the input bus; 
 one or more power busses connected to receive power from the one or more bus converter circuits; 
 a plurality of regulators, each having an input connected to receive power from the one or more power busses and an output for delivering a regulated output; and 
 one or more semiconductor processors connected to receive power from one or more of the plurality of regulators. 
 
     
     
       33. The apparatus of  claim 4 , wherein the voltage across the first ZVS switch is reduced to nearly zero before the first ZVS switch is turned ON and the voltage across the second ZVS switch is reduced to nearly zero before the second ZVS switch is turned ON. 
     
     
       34. The apparatus of  claim 1 , wherein the voltage across the first ZVS switch is reduced to nearly zero before the first ZVS switch is turned ON and the voltage across the second ZVS switch is reduced to nearly zero before the second ZVS switch is turned ON. 
     
     
       35. The apparatus of  claim 1 , wherein at least one of the windings is coupled to the input and at least one of the windings is coupled to the output during the power transfer intervals. 
     
     
       36. The apparatus of  claim 35 , wherein the first winding is coupled to the input during the first power transfer interval and the second winding is coupled to the output during the first power transfer interval. 
     
     
       37. The apparatus of  claim 36 , wherein the transformer comprises a third winding and the third winding is coupled to the output during the second power transfer interval. 
     
     
       38. The apparatus of  claim 1 , wherein the bus converter circuit is a self-contained assembly adapted to be installed as a unit. 
     
     
       39. The apparatus of  claim 38 , wherein the direction is the first direction. 
     
     
       40. The apparatus of  claim 6 , wherein the respective load comprises a computer processor. 
     
     
       41. The apparatus of  claim 1 , wherein the first series circuit comprises one or more of the following: (a) at least one component that is not in the second series circuit, (b) at least one component that is in the second series circuit but is connected in an order that is different from in the second series circuit, or (c) at least one component that is in the second series circuit but is connected to carry a current that flows in a direction that is opposite from a current that the component carries in the second series circuit. 
     
     
       42. A computer apparatus, comprising:
 a power distribution system including an input bus for receiving power at a relatively high safe voltage, preferably approximately 48 Volts; 
 one or more bus converter circuits of  claim 41 , connected to receive power from the input bus; 
 one or more power busses connected to receive power from the one or more bus converter circuits; 
 a plurality of regulators, each having an input connected to receive power from the one or more power busses and an output for delivering a regulated output; and 
 one or more semiconductor processors connected to receive power from one or more of the plurality of regulators. 
 
     
     
       43. The apparatus of  claim 1 , wherein the first set of switches includes one or more switches that are not in the second set of switches. 
     
     
       44. The apparatus of  claim 1 , wherein the first set of switches does not include any switches that are in the second set of switches. 
     
     
       45. The apparatus of  claim 1 , wherein at least one winding of the first series circuit is different than at least one winding of the second series circuit. 
     
     
       46. The apparatus of  claim 1 , wherein at least one winding of the first series circuit is the same as at least one winding of the second series circuit. 
     
     
       47. The apparatus of  claim 46 , wherein the at least one winding is configured in the first series circuit to carry current in one direction and in the second series circuit to carry current in another direction opposite to the one direction. 
     
     
       48. The apparatus of  claim 46 , wherein the first series circuit and the second series circuit each comprises at least two windings of the transformer. 
     
     
       49. A computer apparatus, comprising:
 a power distribution system including an input bus for receiving power at a relatively high safe voltage, preferably approximately 48 Volts; 
 one or more bus converter circuits of  claim 41 , connected to receive power from the input bus; 
 one or more power busses connected to receive power from the one or more bus converter circuits; 
 a plurality of regulators, each having an input connected to receive power from the one or more power busses and an output for delivering a regulated output; and 
 one or more semiconductor processors connected to receive power from one or more of the plurality of regulators. 
 
     
     
       50. The apparatus of  claim 49 , wherein the bus converter circuit is a self-contained assembly adapted to be installed as a unit. 
     
     
       51. The apparatus of  claim 48 , wherein the at least two windings in the first and second series circuits each comprises the first winding and the second winding, and the first winding and the second winding are configured in the first series circuit to carry current in one direction and are configured in the second series circuit to carry current in another direction opposite to the one direction. 
     
     
       52. The apparatus of  claim 51 , wherein the first and second windings are configured in a first order in the first series circuit and in a second different order in the second series circuit. 
     
     
       53. The apparatus of  claim 52 , wherein the first and second windings are configured in the first series circuit for current to flow in the one direction and in the second series circuit for current to flow in the another direction. 
     
     
       54. The apparatus of  claim 51 , wherein the transformer comprises a third winding and the first and second series circuits each further comprise the third winding. 
     
     
       55. The apparatus of  claim 54 , wherein the first, second, and third windings are configured in the first series circuit to carry current in the one direction and in the second series circuit to carry current in the another direction. 
     
     
       56. The apparatus of  claim 54 , wherein the first set of switches does not include any switches that are in the second set of switches. 
     
     
       57. The apparatus of  claim 54 , wherein the first set of switches does not include any switches that are in the second set of switches. 
     
     
       58. The apparatus of  claim 56 , wherein the bus converter circuit is a self-contained assembly adapted to be installed as a unit. 
     
     
       59. The apparatus of  claim 58 , wherein the bus converter circuit is a self-contained assembly adapted to be installed as a unit. 
     
     
       60. The apparatus of  claim 46 , wherein the transformer comprises a third winding and the first series circuit and the second series circuit each comprises at least two windings of the transformer. 
     
     
       61. A computer apparatus, comprising:
 a power distribution system including an input bus for receiving power at a relatively high safe voltage, preferably approximately 48 Volts; 
 one or more bus converter circuits of  claim 60 , connected to receive power from the input bus; 
 one or more power busses connected to receive power from the one or more bus converter circuits; 
 a plurality of regulators, each having an input connected to receive power from the one or more power busses and an output for delivering a regulated output; and 
 one or more semiconductor processors connected to receive power from one or more of the plurality of regulators. 
 
     
     
       62. The apparatus of  claim 61 , wherein one or more of the bus converter circuits is a self-contained assembly adapted to be installed as a unit. 
     
     
       63. The apparatus of  claim 1 , wherein the first winding and the second winding are connected together at a node and the second terminal is connected to receive power from the node. 
     
     
       64. The apparatus of  claim 63 , wherein the first winding and the second winding comprise an equal number of turns and the bus converter circuit is further capable of converting power in either the first direction or the second direction. 
     
     
       65. The apparatus of  claim 64 , wherein the transformer further comprises a third winding, and the first and second series circuits each include at least two windings. 
     
     
       66. The apparatus of  claim 1 , wherein the first winding and second winding are connected together at a node and the common terminal is connected to the node. 
     
     
       67. The apparatus of  claim 66 , wherein the first winding and the second winding comprise an equal number of turns, and the bus converter circuit is further capable of converting power in either the first direction or a second opposite direction. 
     
     
       68. A method, comprising:
 providing a bus converter circuit having a first terminal, a second terminal, and a common terminal and being configured to convert power in a direction, the direction being one of the following:
 (a) a first direction in which the first terminal and common terminal form an input for receiving input power at a first voltage, V1, and the second terminal and the common terminal form an output for delivering output power at a second voltage, V2, or 
 (b) a second direction in which the second terminal and the common terminal form an input for receiving input power at the second voltage, V2, and the first terminal and the common terminal form an output for delivering output power at the first voltage, V1; 
 
 galvanically connecting the input and the output; 
 wherein over a range of input voltages the bus converter circuit a uses an essentially fixed voltage transformation ratio, K, equal to the second voltage, V2 divided by the first voltage, V1, (K=V2/V1), to convert power in the direction, such that output power delivered in the first direction is at the second voltage, V2=K×V1, and output power delivered in the second direction is at the first voltage, V1=V2/K; 
 wherein the first voltage, V1, is greater than the second voltage, V2; 
 wherein the bus converter circuit includes (i) a transformer having a first winding and a second winding, (ii) a plurality of switches, and (iii) a controller; 
 operating, by the controller, the plurality of switches in a series of converter operating cycles including a first and a second power transfer interval, the first and second power transfer intervals having essentially equal durations, and wherein during the first power transfer interval a first set of the plurality of switches is ON and power is converted in the direction, and during the second power transfer interval a second set of the plurality of switches is ON and power is converted in the direction; 
 forming, by the bus converter circuit, during the first power transfer interval a first series circuit in which at least the following elements are all connected in series without regard to order: at least one of the first or second terminals, at least one of the first or second windings of the transformer, at least one of the plurality of switches in the first set, and at least one capacitor, and conducting, by the bus converter circuit, current in the direction between the first terminal and the second terminal; 
 forming, by the bus converter circuit, during the second power transfer interval a second series circuit in which at least the following elements are all connected in series without regard to order: at least one of the first and second terminals, at least one of the first or second windings of the transformer, at least one of the plurality of switches in the second set, and at least one capacitor, and conducting, by the bus converter circuit, current in the direction between the first terminal and the second terminal; 
 before the first power transfer interval, reducing, by the bus converter circuit, a voltage across a first ZVS switch prior to turning the first ZVS switch ON, such that the voltage across the first ZVS switch is reduced when the first ZVS switch is turned ON, the first ZVS switch being at least one of the plurality of switches in the first set; and 
 reducing, by the bus converter circuit, a voltage across a second ZVS switch prior to turning the second ZVS switch ON, such that the voltage across the second ZVS switch is reduced when the second ZVS switch is turned ON, the second ZVS switch being at least one of the plurality of switches in the second set. 
 
     
     
       69. The method of  claim 68 , further comprising providing inrush current control at least during start-up of the bus converter circuit. 
     
     
       70. The method of  claim 68 , further comprising providing the bus converter circuit as a self-contained assembly. 
     
     
       71. The method of  claim 68 , wherein forming the first and second series circuits includes at least two of the first and second terminals. 
     
     
       72. The method of  claim 71 , wherein the bus converter circuit is capable of converting power in either of the first direction or the second direction and the direction is a function of conditions external to the bus converter circuit. 
     
     
       73. The method of  claim 71 , wherein at least one winding of the first series circuit is the same as at least one winding of the second series circuit; and the at least one winding of the first series circuit is connected to carry current in one direction and the at least one winding of the second series circuit is connected to carry current in another direction opposite to the one direction. 
     
     
       74. The method of  claim 71 , wherein at least one winding of the first series circuit is different than at least one winding of the second series circuit. 
     
     
       75. The method of  claim 74 , comprising connecting the first, second, and third windings in the first series circuit to carry current in one direction and in the second series circuit to carry current in another direction opposite to the one direction. 
     
     
       76. The method of  claim 71 , wherein the voltage across the first ZVS switch is reduced to nearly zero before the first ZVS switch is turned ON and the voltage across the second ZVS switch is reduced to nearly zero before the second ZVS switch is turned ON. 
     
     
       77. The method of  claim 68 , wherein the first series circuit and the second series circuit each comprises at least two windings of the transformer. 
     
     
       78. The method of  claim 77 , comprising:
 connecting the first winding and the second winding in the first series circuit to carry current in the one direction; and 
 connecting the first winding and the second winding in the second series circuit to carry current in the another direction. 
 
     
     
       79. The method of  claim 77 , comprising connecting the first and second windings in a first order in the first series circuit and in a second different order in the second series circuit. 
     
     
       80. The method of  claim 77 , wherein the first and second series circuits include the first and second terminals. 
     
     
       81. The method of  claim 80 , wherein the transformer comprises a third winding and the first and second series circuits each further comprises the third winding. 
     
     
       82. The apparatus of  claim 68 , wherein the first and second series circuits form a first and a second series resonant circuit, each having a characteristic resonant period; and the essentially equal duration of the first and second power transfer intervals is less than each characteristic resonant period. 
     
     
       83. The method of  claim 68 , wherein the voltage across the first ZVS switch is reduced to nearly zero before the first ZVS switch is turned ON and the voltage across the second ZVS switch is reduced to nearly zero before the second ZVS switch is turned ON. 
     
     
       84. The method of  claim 68 , further comprising:
 providing an input power bus connected to supply power to the input of the bus converter circuit; 
 providing a power distribution bus connected to receive power at a relatively high safe voltage, preferably approximately 48 Volts, from the output of the bus converter circuit; 
 providing a plurality of regulators, each having an input connected to receive power from the power distribution bus and an output for delivering a regulated output; and 
 one or more semiconductor processors connected to receive power from one or more of the plurality of regulators. 
 
     
     
       85. A method of powering a computer processor, the method comprising:
 using an input bus to distribute input power at a first voltage, V1; 
 using one or more non-isolated bus converters to convert power received from the input bus for delivery to an output at a second voltage, V2; 
 using one or more output power busses to distribute power from the one or more bus converters at the second voltage, V2, to one or more loads; 
 using a plurality of regulators to regulate power received from the output power busses for delivery via a regulator output to the one or more loads; and 
 wherein one or more of the loads comprise a computer processor; 
 wherein the one or more non-isolated bus converters have a first terminal, a second terminal, and a common terminal, and the first terminal and common terminal form an input connected to receive power from the input bus at the first voltage, V1, and the second terminal and the common terminal form an output for delivering output power at the second voltage, V2, to the one or more power busses; 
 wherein the input is galvanically connected to the output; 
 using an essentially fixed voltage transformation ratio, K, equal to the second voltage, V2 divided by the first voltage, V1, (K=V2/V1), to convert power in the one or more bus converters from the input for delivery to the output at the second voltage, V2=K×V1, over a range of input voltages; 
 wherein the first voltage, V1, is greater than the second voltage, V2; 
 wherein the one or more non-isolated bus converters include (i) a transformer having a first winding and a second winding, (ii) a plurality of switches, and (iii) a controller; 
 using the controller to operate the plurality of switches in a series of converter operating cycles including a first and a second power transfer interval, the first and second power transfer intervals having essentially equal durations, and wherein during the first power transfer interval a first set of the plurality of switches is ON and power is converted from the input to the output, and during the second power transfer interval a second set of the plurality of switches is ON and power is converted from the input to the output; 
 wherein the one or more non-isolated bus converters are configured, during the first power transfer interval to (a) form a first series circuit in which at least the following elements are all connected in series without regard to order: at least one of the first or second terminals, at least one of the first or second windings of the transformer, at least one of the plurality of switches in the first set, and at least one capacitor, and (b) convert current flowing through the first terminal into current flowing through the second terminal in inverse proportion to the essentially fixed voltage transformation ratio, K; 
 wherein the one or more non-isolated bus converters are configured during the second power transfer interval to (a) form a second series circuit in which at least the following elements are all connected in series without regard to order: at least one of the first and second terminals, at least one of the first or second windings of the transformer, at least one of the plurality of switches in the second set, and at least one capacitor, and (b) convert current flowing through the first terminal into current flowing through the second terminal in inverse proportion to the essentially fixed voltage transformation ratio, K; 
 wherein the one or more non-isolated bus converters are configured before the first power transfer interval, to reduce a voltage across a first ZVS switch prior to turning the first ZVS switch ON, such that the voltage across the first ZVS switch is reduced when the first ZVS switch is turned ON, the first ZVS switch being at least one of the plurality of switches in the first set; and 
 wherein the one or more non-isolated bus converters are configured before the second power transfer interval, to reduce a voltage across a second ZVS switch prior to turning the second ZVS switch ON, such that the voltage across the second ZVS switch is reduced when the second ZVS switch is turned ON, the second ZVS switch being at least one of the plurality of switches in the second set. 
 
     
     
       86. The method of  claim 85 , further comprising converting power from an AC utility line for delivery at a DC voltage, the converting providing voltage step down and galvanic isolation to provide a relatively high safe voltage, preferably approximately 48 Volts and wherein the first voltage, V1, is approximately 48 Volts. 
     
     
       87. The method of  claim 85 , wherein the first winding and the second winding are connected together at a node and further comprising delivering power via the node to the second terminal. 
     
     
       88. The method of  claim 87 , wherein the first winding comprises a first number of turns and the second winding comprise a second number of turns, and the first number and second number are equal. 
     
     
       89. A computer apparatus comprising:
 a power distribution system including an input bus for receiving power at a relatively high safe voltage, preferably approximately 48 Volts; 
 one or more bus converter circuits connected to receive power from the input bus; 
 one or more power busses connected to receive power from the one or more bus converter circuits; 
 a plurality of regulators, each having an input connected to receive power from the one or more power busses and an output for delivering a regulated output; and 
 one or more semiconductor processors connected to receive power from one or more of the regulators; 
 wherein at least one of the one or more bus converter circuits has a first terminal, a second terminal, and a common terminal and is configured to convert power in a first direction in which the first terminal and common terminal form an input for receiving input power at a first voltage, V1, and the second terminal and the common terminal form an output for delivering output power at a second voltage, V2; 
 wherein the input and output are galvanically connected; 
 wherein over a range of input voltages the at least one of the one or more bus converter circuits uses an essentially fixed voltage transformation ratio, K, equal to the second voltage, V2 divided by the first voltage, V1, (K=V2/V1), to convert power in the first direction, such that output power delivered is at the second voltage, V2=K×V1; 
 wherein the first voltage, V1, is greater than the second voltage, V2; 
 wherein the at least one of the one or more bus converter circuits includes (i) a transformer having a first winding and a second winding, (ii) a plurality of switches, and (iii) a controller configured to operate the plurality of switches in a series of converter operating cycles; 
 wherein each converter operating cycle includes a first and a second power transfer interval, the first and second power transfer intervals having essentially equal durations, and wherein during the first power transfer interval a first set of the plurality of switches is ON and power is converted in the first direction, and during the second power transfer interval a second set of the plurality of switches is ON and power is converted in the first direction; 
 wherein the at least one of the one or more bus converter circuits is configured during the first power transfer interval to (a) form a first series circuit in which at least the following elements are all connected in series without regard to order: at least one of the first or second terminals, at least one of the first or second windings of the transformer, at least one of the plurality of switches in the first set, and at least one capacitor, and (b) convert in the first direction current flowing through the first terminal into current flowing through the second terminal in inverse proportion to the essentially fixed voltage transformation ratio, K; 
 wherein the at least one of the one or more bus converter circuits is configured during the second power transfer interval to (a) form a second series circuit in which at least the following elements are all connected in series without regard to order: at least one of the first or second terminals, at least one of the first or second windings of the transformer, at least one of the plurality of switches in the second set, and at least one capacitor, and (b) convert in the first direction current flowing through the first terminal into current flowing through the second terminal in inverse proportion to the essentially fixed voltage transformation ratio, K; 
 wherein the at least one of the one or more bus converter circuits is configured to, before the first power transfer interval, reduce a voltage across a first ZVS switch prior to turning the first ZVS switch ON, such that the voltage across the first ZVS switch is reduced when the first ZVS switch is turned ON, the first ZVS switch being at least one of the plurality of switches in the first set; and 
 wherein the at least one of the one or more bus converter circuits is configured to, before the second power transfer interval, reduce a voltage across a second ZVS switch prior to turning the second ZVS switch ON, such that the voltage across the second ZVS switch is reduced when the second ZVS switch is turned ON, the second ZVS switch being at least one of the plurality of switches in the second set. 
 
     
     
       90. The apparatus of  claim 89 , wherein the first series circuit comprises one or more of the following: (a) at least one component that is not in the second series circuit, (b) at least one component that is in the second series circuit but is connected in an order that is different from in the second series circuit, or (c) at least one component that is in the second series circuit but is connected to carry a current that flows in a direction that is opposite from a current that the component carries in the second series circuit. 
     
     
       91. The apparatus of  claim 90 , wherein the first winding and the second winding are connected together at a node and the common terminal is connected to the node. 
     
     
       92. The apparatus of  claim 91 , wherein the first winding and the second winding comprise an equal number of turns and the at least one of the one or more bus converter circuits is further capable of converting power in either the first direction or a second opposite direction. 
     
     
       93. The apparatus of  claim 92 , wherein the transformer further comprises a third winding, and the first and second series circuits each include at least two windings. 
     
     
       94. The apparatus of  claim 1 , wherein the first winding and second winding are connected together at a node and the second terminal is connected to receive power from the node. 
     
     
       95. The apparatus of  claim 93 , wherein the first winding and the second winding comprise an equal number of turns, and the at least one of the one or more bus converter circuits is further capable of converting power in either the first direction or a second opposite direction.