Digital-to-analog converter architecture for audio amplifiers

Abstract

In some embodiments, a digital-to-analog converter (DAC) architecture can include an array having a total number of bit cells, and a control system configured to activate a selected number of the total number of bit cells and to deactivate the remaining bit cells. The selected number can be variable, such that the array consumes a quiescent current that depends on the selected number. The control system can be further configured to change the selected number when a signal condition exceeds a threshold duration.

What is claimed is: 
     
       1. A digital-to-analog converter (DAC) architecture comprising:
 an array having a total number of bit cells; and 
 a control system configured to activate a selected number of the total number of bit cells and to deactivate the remaining bit cells, the selected number being variable, such that the array consumes a quiescent current that depends on the selected number, the control system further configured to change the selected number when a signal condition exceeds a threshold duration, the DAC architecture being configured to convert a digital signal stream into a respective analog audio signal stream, and the control system including a variable length shifter implemented to perform a shifting operation among the selected number of active bit cells. 
 
     
     
       2. The DAC architecture of  claim 1  wherein the control system selects a low value for the selected number when a low resolution is sufficient, such that the array consumes a low amount of quiescent current when the selected number is low. 
     
     
       3. The DAC architecture of  claim 1  wherein the control system selects a high value for the selected number when a high resolution is desired, such that the array consumes a high amount of quiescent current when the selected number is high. 
     
     
       4. The DAC architecture of  claim 1  wherein the control system further includes a scrambling network implemented to be driven by the variable length shifter. 
     
     
       5. The DAC architecture of  claim 4  wherein the scrambling network is implemented as a butterfly or Benes network fed by a linear-feedback shift register. 
     
     
       6. The DAC architecture of  claim 1  wherein the control system is configured such that the threshold duration includes a first threshold duration for increasing the selected number, and a second threshold duration for decreasing the selected number. 
     
     
       7. The DAC architecture of  claim 6  wherein the first threshold duration is approximately equal to the second threshold duration. 
     
     
       8. The DAC architecture of  claim 6  wherein the first threshold duration is different than the second threshold duration. 
     
     
       9. The DAC architecture of  claim 6  wherein the first threshold duration is selected to avoid an increase in the selected number due to an occasional noise. 
     
     
       10. The DAC architecture of  claim 6  wherein the second threshold duration is selected based on the signal condition remaining below a threshold value for the second threshold duration. 
     
     
       11. The DAC architecture of  claim 10  wherein the second threshold duration is selected to avoid a decrease in the selected number due to a constant AC signal. 
     
     
       12. The DAC architecture of  claim 1  wherein the control system is configured to utilize either or both of time and level hysteresis to avoid or reduce an audible artifact resulting from a gain change associated with a dynamic change in the number of active bit cells. 
     
     
       13. The DAC architecture of  claim 1  wherein the variable length shifter includes a barrel shifter configured to perform a barrel shifting operation as the shifting operation. 
     
     
       14. A method for converting a digital signal to an analog signal in a digital-to-analog converter (DAC) architecture, the method comprising:
 providing an array with a total number of bit cells; and 
 controlling the array to activate a selected number of the total number of bit cells and to deactivate the remaining bit cells, the selected number being variable, such that the array consumes a quiescent current that depends on the selected number, the controlling further including changing the selected number when a signal condition exceeds a threshold duration, the controlling further including a variable length shifting operation among the selected number of active bit cells, such that the DAC architecture converts a digital signal stream into a respective analog audio signal stream. 
 
     
     
       15. A wireless device comprising:
 an antenna for receiving a wireless signal; 
 a driver configured to convert a digital signal representative of the received wireless signal into an analog signal with a digital-to-analog converter (DAC) system, the DAC system including an array having a total number of bit cells, the DAC system further including a control system configured to activate a selected number of the total number of bit cells and to deactivate the remaining bit cells, the selected number being variable, such that the array consumes a quiescent current that depends on the selected number, the control system further configured to change the selected number when a signal condition exceeds a threshold duration, the control system including a variable length shifter implemented to perform a shifting operation among the selected number of active bit cells; and 
 a speaker in communication with the driver and configured to generate sound waves based on the analog signal. 
 
     
     
       16. The wireless device of  claim 14  wherein the wireless device is a wireless headphone or a wireless earphone. 
     
     
       17. The wireless device of  claim 15  wherein the variable length shifter includes a barrel shifter configured to perform a barrel shifting operation as the shifting operation.