Sealing ring, stacked structure, and method for manufacturing sealing ring

Abstract

Embodiments of the disclosure provide a sealing ring, a stacked structure, and a method for manufacturing a sealing ring. The sealing ring is arranged at a periphery of a device area of a chip, and includes an inner ring structure, a middle ring structure, and an outer ring structure. The middle ring structure is connected to the device area through a doped well. The doped well is located in part of a substrate corresponding to the inner ring structure and the middle ring structure, and is isolated from the inner ring structure.

The invention claimed is: 
     
       1. A sealing ring, arranged at a periphery of a device area of a chip, wherein the sealing ring comprises an inner ring structure, a middle ring structure, and an outer ring structure;
 wherein the middle ring structure is connected to the device area through a doped well; and the doped well is located in part of a substrate corresponding to the inner ring structure and the middle ring structure, and is isolated from the inner ring structure; 
 wherein the substrate comprises a first surface and a second surface that are opposite to each other; the doped well is located in the first surface; and the middle ring structure comprises a first middle ring structure and a second middle ring structure; 
 wherein the first middle ring structure is arranged in a first dielectric layer on the first surface of the substrate, and the second middle ring structure is arranged in a second dielectric layer on the second surface of the substrate; 
 wherein the first middle ring structure comprises a plurality of metal layers, a via connecting the metal layer, and a metal plug connecting the substrate and the metal layer; 
 wherein the first surface of the substrate further comprises a plurality of isolation areas and active areas that are arranged at intervals; and 
 the metal plug of the first middle ring structure comprises a first metal plug and a second metal plug, wherein the first metal plug is configured to connect one of the active areas and a first metal layer of the plurality of metal layers, and the second metal plug is configured to connect the doped well and a second metal layer of the plurality of metal layers. 
 
     
     
       2. The sealing ring of  claim 1 , wherein the device area is provided with a test circuit; and
 the middle ring structure is electrically connected to the test circuit through the doped well. 
 
     
     
       3. The sealing ring of  claim 2 , wherein the sealing ring is arranged in a stacked structure, and the stacked structure comprises at least a first chip and a second chip that are stacked in sequence;
 the first middle ring structure of the second chip is electrically connected to the test circuit through the doped well. 
 
     
     
       4. The sealing ring of  claim 3 , wherein the device area is further provided with a silicon via; and
 the test circuit is connected to a surface of a topmost chip in the stacked structure through the silicon via. 
 
     
     
       5. The sealing ring of  claim 3 , wherein the second middle ring structure of the first chip is connected to the first middle ring structure of the second chip. 
     
     
       6. The sealing ring of  claim 1 , wherein
 the first metal layer of the first middle ring structure is not connected to the second metal layer of the first middle ring structure. 
 
     
     
       7. The sealing ring of  claim 6 , wherein the inner ring structure comprises a first inner ring structure arranged in the first dielectric layer and a second inner ring structure arranged in the second dielectric layer; and
 the outer ring structure comprises a first outer ring structure arranged in the first dielectric layer and a second outer ring structure arranged in the second dielectric layer. 
 
     
     
       8. The sealing ring of  claim 7 , wherein the first inner ring structure has a same structure as the first outer ring structure; and
 the first inner ring structure comprises a plurality of metal layers, a via connecting the metal layer, and a metal plug connecting the substrate and a third metal layer of the plurality of metal layers. 
 
     
     
       9. The sealing ring of  claim 8 , wherein the metal plug of the first inner ring structure is arranged at one of the plurality of isolation areas, and the metal plug of the first outer ring structure is arranged at another one of the active areas. 
     
     
       10. The sealing ring of  claim 7 , wherein the second inner ring structure, the second middle ring structure, and the second outer ring structure have a same structure; and
 the second inner ring structure comprises at least two metal layers and a via connecting the adjacent metal layers. 
 
     
     
       11. A stacked structure, comprising a plurality of chips that are bonded back-to-face in sequence, wherein each chip comprises at least the sealing ring of  claim 1 . 
     
     
       12. A method for manufacturing a sealing ring arranged at a periphery of a device area of a chip, comprising:
 forming a doped well in a substrate of the chip; 
 forming an inner ring structure, a middle ring structure, and an outer ring structure around the device area on a surface of the substrate, wherein the sealing ring is formed by the inner ring structure, the middle ring structure, and the outer ring structure; the middle ring structure is connected to the device area through the doped well; and the doped well is located in part of the substrate corresponding to the inner ring structure and the middle ring structure, and is isolated from the inner ring structure; 
 forming a plurality of isolation areas and active areas that are arranged at intervals on the first surface of the substrate, before or after the doped well is formed; wherein the doped well is isolated from the inner ring structure through at least one of the plurality of isolation areas; 
 wherein the forming the inner ring structure, the middle ring structure, and the outer ring structure around the device area on the surface of the substrate comprises: respectively forming the inner ring structure, the middle ring structure, and the outer ring structure around the device area on a first surface of the substrate and a second surface of the substrate, wherein the first surface is arranged opposite to the second surface, and the doped well is located in the first surface; 
 wherein the inner ring structure comprises at least a first inner ring structure located in the first surface of the substrate, the middle ring structure comprises at least a first middle ring structure located in the first surface of the substrate, the outer ring structure comprises at least a first outer ring structure located in the first surface of the substrate; 
 wherein the forming the inner ring structure, the middle ring structure, and the outer ring structure on the first surface of the substrate comprises: forming a first dielectric layer on the first surface of the substrate; and forming the first inner ring structure, the first middle ring structure, and the first outer ring structure in the first dielectric layer; 
 wherein the forming the first inner ring structure, the first middle ring structure, and the first outer ring structure in the first dielectric layer comprises: 
 etching the first dielectric layer to form a plurality of first etching holes, wherein one first etching hole of the first inner ring structure allows a surface of one of the isolation areas to be exposed, one first etching hole of the first middle ring structure allows a surface of the active areas to be exposed and another first etching hole of the first middle ring structure allows a surface of the doped well to be exposed, and one first etching hole of the first outer ring structure allows a surface of another one of the active areas to be exposed; 
 filling a first metal material in each first etching hole to form a metal plug; and 
 forming a plurality of metal layers and a via connecting the metal layers on a surface of each metal plug. 
 
     
     
       13. The method of  claim 12 , wherein the inner ring structure further comprises a second inner ring structure located in the second surface of the substrate, the middle ring structure further comprises a second middle ring structure located in the second surface of the substrate; the outer ring structure further comprises a second outer ring structure located in the second surface of the substrate;
 a second dielectric layer is formed on the second surface of the substrate; and 
 the second inner ring structure, the second middle ring structure, and the second outer ring structure are formed in the second dielectric layer. 
 
     
     
       14. The method of  claim 13 , wherein forming the second inner ring structure, the second middle ring structure, and the second outer ring structure in the second dielectric layer comprises:
 etching the second dielectric layer to form a plurality of second etching holes; 
 filling a second metal material in each second etching hole to respectively form the first metal layer of the second inner ring structure, the second middle ring structure, and the second outer ring structure; and 
 forming at least one second metal layer and a via connecting the first metal layer and the second metal layer on a surface of the first metal layer. 
 
     
     
       15. The method of  claim 12 , further comprising:
 forming a test circuit in the first dielectric layer on a surface of the device area, 
 wherein the first middle ring structure is electrically connected to the test circuit through the doped well. 
 
     
     
       16. The method of  claim 15 , wherein the sealing ring is arranged in a stacked structure comprising a plurality of chips that are stacked in sequence,
 the method further comprising: forming a silicon via structure at the device area; 
 wherein the test circuit is connected to a surface of a topmost chip in the stacked structure through the silicon via.