Programmable traffic ingress direction for reduced latency in a DPU

Abstract

Embodiments herein describe selectively bypassing a networking pipeline in a DPU. For example, instead of a packet being processed by both the networking pipeline and a DMA pipeline in the DPU, the packet is only processed by the DMA pipeline. This can reduce latency for packets that do not have network-heavy tasks associated with them, such Remote Direct Memory Access (RDMA) over Converged Ethernet (RoCE) packets. In addition, the DPU can perform load balancing between different instances of the pipelines in the DPU.

What is claimed is: 
     
       1. A data processing unit (DPU), comprising:
 a networking pipeline; 
 a direct memory access (DMA) pipeline; 
 a parser circuit configured to parse a received packet to identify a packet header vector (PHV); and 
 match circuitry configured to, based on receiving the PHV:
 determine that the received packet should bypass the networking pipeline; and 
 edit the PHV to indicate the received packet should be transmitted to the DMA pipeline. 
 
 
     
     
       2. The DPU of  claim 1 , wherein the match circuitry is configured to:
 edit the PHV to include commands; and 
 provide the edited PHV to a packet editor in the DPU. 
 
     
     
       3. The DPU of  claim 2 , wherein the packet editor comprises circuitry configured to:
 perform the commands to edit a header of the received packet; and 
 forward the received packet with the edited header to the DMA pipeline, wherein the received packet is not processed by any networking pipeline in the DPU. 
 
     
     
       4. The DPU of  claim 3 , wherein the parser circuit is configured to parse a second received packet to identify a second PHV,
 wherein the match circuitry is configured to, based on receiving the second PHV, determine that the second received packet should not bypass the networking pipeline, 
 wherein the packet editor is configured to forward the second received packet to the networking pipeline, wherein the networking pipeline is configured to forward the second received packet to the DMA pipeline when finished processing the second received packet. 
 
     
     
       5. The DPU of  claim 4 , further comprising:
 a plurality of networking pipelines which includes the networking pipeline; and 
 a plurality of DMA pipelines which includes the DMA pipeline, 
 wherein the match circuitry is configured to, based on the PHV, edit the PHV to indicate that the networking pipeline should receive the second received packet to perform load balancing between the plurality of networking pipelines. 
 
     
     
       6. The DPU of  claim 1 , wherein the match circuitry comprises:
 a table memory; 
 a table engine comprising circuitry configured to perform a lookup into the table memory using data in the PHV; and 
 a match processing unit (MPU) comprising circuitry configured to determine that the received packet should not bypass the networking pipeline using results of the lookup into the table memory and to edit the PHV to indicate the received packet should be transmitted to the DMA pipeline. 
 
     
     
       7. The DPU of  claim 6 , wherein the lookup into the table memory returns results that depend on state information stored in the table memory, wherein the state information comprises one or more policers for performing rate limiting. 
     
     
       8. A method comprising:
 parsing a received packet to identify a packet header vector (PHV); 
 determining that the received packet should bypass a networking pipeline based on data in the PHV; and 
 editing the PHV to indicate the received packet should be transmitted to a DMA pipeline rather than the networking pipeline. 
 
     
     
       9. The method of  claim 8 , further comprising:
 editing, before transmitting the received packet to the DMA pipeline, the PHV to include commands; 
 performing the commands to edit a header of the received packet; and 
 forwarding, after the commands have been performed, the received packet with the edited header to the DMA pipeline, wherein the received packet is not processed by any networking pipeline. 
 
     
     
       10. The method of  claim 8 , further comprising:
 parsing a second received packet to identify a second PHV; 
 determining, based on the second PHV, that the second received packet should not bypass the networking pipeline; and 
 forwarding the second received packet to the networking pipeline; and 
 forwarding the second received packet to the DMA pipeline when the networking pipeline is finished processing the second received packet. 
 
     
     
       11. The method of  claim 10 , further comprising, before forwarding the second received packet to the networking pipeline:
 determining, based on the second PHV, which of a plurality of networking pipelines should receive the second received packet to perform load balancing. 
 
     
     
       12. The method of  claim 8 , wherein determining that the received packet should bypass the networking pipeline based on data in the PHV is performed by a MPU in a DPU. 
     
     
       13. The method of  claim 12 , wherein the DPU is in a network interface controller/card (NIC). 
     
     
       14. A network interface card (NIC), comprising:
 a networking pipeline; 
 a DMA pipeline; 
 a parser circuit configured to parse a received packet to identify a packet header vector (PHV); and 
 match circuitry configured to, based on receiving the PHV: 
 determine that the received packet should bypass the networking pipeline; and 
 edit the PHV to indicate the received packet should be transmitted to the DMA pipeline. 
 
     
     
       15. The NIC of  claim 14 , wherein the match circuitry is configured to:
 edit the PHV to include commands; and 
 provide the edited PHV to a packet editor in the NIC. 
 
     
     
       16. The NIC of  claim 15 , wherein the packet editor comprises circuitry configured to:
 perform the commands to edit a header of the received packet; and 
 forward the received packet with the edited header to the DMA pipeline, wherein the received packet is not processed by any networking pipeline in the NIC. 
 
     
     
       17. The NIC of  claim 16 , wherein the parser circuit is configured to parse a second received packet to identify a second PHV,
 wherein the match circuitry is configured to, based on receiving the second PHV, determine that the second received packet should not bypass the networking pipeline, 
 wherein the packet editor is configured to forward the second received packet to the networking pipeline, wherein the networking pipeline is configured to forward the second received packet to the DMA pipeline when finished processing the second received packet. 
 
     
     
       18. The NIC of  claim 17 , further comprising:
 a plurality of networking pipelines which includes the networking pipeline; and 
 a plurality of DMA pipelines which includes the DMA pipeline, 
 wherein the match circuitry is configured to, based on the PHV, edit the PHV to indicate that the networking pipeline should receive the second received packet to perform load balancing between the plurality of networking pipelines. 
 
     
     
       19. The NIC of  claim 14 , wherein the match circuitry comprises:
 a table memory; 
 a table engine comprising circuitry configured to perform a lookup into the table memory using data in the PHV; and 
 a MPU comprising circuitry configured to determine that the received packet should not bypass the networking pipeline using results of the lookup into the table memory and to edit the PHV to indicate the received packet should be transmitted to the DMA pipeline. 
 
     
     
       20. The NIC of  claim 19 , wherein the lookup into the table memory returns results that depend on state information stored in the table memory, wherein the state information comprises one or more policers for performing rate limiting.