Location-based global cache tiering

Abstract

A method for use in a storage processor, comprising: generating or updating a cache metadata table that identifies a plurality of cache slots, for each of the plurality of cache slots, the cache metadata table including a different respective location identifier that indicates a location for that cache slot; receiving an I/O request that is associated with a logical block address; allocating a given one of the plurality of cache slots to the logical block address based on the respective location identifier that corresponds to the given cache slot; and executing the I/O request by using the given cache slot, wherein using the given cache slot includes identifying a memory address that is associated with the cache slot and executing at least one direct memory access (DMA) command based on the memory address.

The invention claimed is: 
     
       1. A method for use in a storage processor, comprising:
 generating or updating a cache metadata table that identifies a plurality of cache slots, for each of the plurality of cache slots, the cache metadata table including a different respective location identifier that indicates a location for that cache slot; 
 receiving an I/O request that is associated with a logical block address; 
 allocating a given one of the plurality of cache slots to the logical block address based on the respective location identifier that corresponds to the given cache slot; and 
 executing the I/O request by using the given cache slot, wherein using the given cache slot includes identifying a memory address that is associated with the cache slot and executing at least one direct memory access (DMA) command based on the memory address, 
 wherein the cache metadata table includes a global memory cache table for a storage system of which the storage processor is part, and at least some of the plurality of cache slots are resident in random access memory modules of other storage processors that are part of the storage system, 
 wherein identified memory address is a global memory address belonging to a memory namespace that encompasses multiple storage processors in the storage system, 
 wherein allocating the given cache slot includes obtaining an identifier of a host device that is associated with the I/O request, and retrieving a location-based policy that corresponds to the host device, and 
 wherein the given cache slot is allocated based on both the location-based policy and the respective location identifier of the given cache slot. 
 
     
     
       2. The method of  claim 1 , wherein allocating the given cache slot based on the respective location identifier of the given cache slot m includes allocating one of the plurality of slots that is situated within a predetermined geographic distance from the storage processor. 
     
     
       3. The method of  claim 1 , wherein at least one of the plurality of cache slots is resident in a storage controller memory buffer of a solid state drive (SSD). 
     
     
       4. The method of  claim 1 , wherein at least one of the plurality of cache slots is part of a persistent memory region of an SSD. 
     
     
       5. The method of  claim 1 , wherein:
 the given cache slot is resident in a volatile memory of an SSD, and 
 executing the DMA command includes identifying a parallel computing interface (PCI) address for a portion of the volatile memory of the SSD and using the identified PCI address to execute the DMA command, the PCI address being identified based on the memory address. 
 
     
     
       6. The method of  claim 5 , wherein the SSD is one of:
 an SSD that is situated in a same enclosure as the storage processor and plugged into an M.2 slot that is provided in a motherboard of the storage processor; 
 an SSD that is external to the storage processor and coupled to the storage processor via an InfiniBand adapter of the storage processor; and 
 an SSD that is external to the storage processor and coupled to the storage processor via a backplane of a server enclosure in which the storage processor is situated. 
 
     
     
       7. A computing device, comprising:
 a memory; and 
 at least one processor that is operatively coupled to the memory, the at least one processor being configured to perform the operations of:
 generating or updating a cache metadata table that identifies a plurality of cache slots, for each of the plurality of cache slots, the cache metadata table including a different respective location identifier that indicates a location for that cache slot; 
 receiving an I/O request that is associated with a logical block address; 
 allocating a given one of the plurality of cache slots to the logical block address based on the respective location identifier that corresponds to the given cache slot; and 
 executing the I/O request by using the given cache slot, wherein using the given cache slot includes identifying a memory address that is associated with the cache slot and executing at least one direct memory access (DMA) command based on the memory address, 
 
 wherein the cache metadata table includes a global memory cache table for a storage system of which the computing device is part, and at least some of the plurality of cache slots are resident in random access memory modules of other computing devices that are part of the storage system, 
 wherein identified memory address is a global memory address belonging to a memory namespace that encompasses multiple computing devices in the storage system, 
 wherein allocating the given cache slot includes obtaining an identifier of a host device that is associated with the I/O request, and retrieving a location-based policy that corresponds to the host device, and 
 wherein the given cache slot is allocated based on both the location-based policy and the respective location identifier of the given cache slot. 
 
     
     
       8. The computing device of  claim 7 , wherein allocating the given cache slot based on the respective location identifier of the given cache slot and the location-based policy includes allocating one of the plurality of slots that is situated within a predetermined geographic distance from the computing device. 
     
     
       9. The computing device of  claim 7 , wherein at least one of the plurality of cache slots is resident in a storage controller memory buffer of a solid state drive (SSD). 
     
     
       10. The computing device of  claim 7 , wherein at least one of the plurality of cache slots is part of a persistent memory region of an SSD. 
     
     
       11. The computing device of  claim 7 , wherein:
 the given cache slot is resident in a volatile memory of an SSD, and 
 executing the DMA command includes identifying a parallel computing interface (PCI) address for a portion of the volatile memory of the SSD and using the identified PCI address to execute the DMA command, the PCI address being identified based on the memory address. 
 
     
     
       12. The computing device of  claim 11 , wherein the SSD is one of:
 an SSD that is situated in a same enclosure as the computing device and plugged into an M.2 slot that is provided in a motherboard of the computing device; 
 an SSD that is external to the computing device and coupled to the computing device via an InfiniBand adapter of the computing device; and 
 an SSD that is external to the computing device and coupled to the computing device via a backplane of a server enclosure in which the computing device is situated. 
 
     
     
       13. A non-transitory computer-readable medium storing one or more processor-executable instructions, which, when executed by at least one processor of a computing device, causes the computing device to perform the operations of:
 generating or updating a cache metadata table that identifies a plurality of cache slots, for each of the plurality of cache slots, the cache metadata table including a different respective location identifier that indicates a location for that cache slot; 
 receiving an I/O request that is associated with a logical block address; 
 allocating a given one of the plurality of cache slots to the logical block address based on the respective location identifier that corresponds to the given cache slot; and 
 executing the I/O request by using the given cache slot, wherein using the given cache slot includes identifying a memory address that is associated with the cache slot and executing at least one direct memory access (DMA) command based on the memory address, 
 wherein the cache metadata table includes a global memory cache table for a storage system of which the computing device is part, and at least some of the plurality of cache slots are resident in random access memory modules of other computing devices that are part of the storage system, 
 wherein identified memory address is a global memory address belonging to a memory namespace that encompasses multiple computing devices in the storage system, 
 wherein allocating the given cache slot includes obtaining an identifier of a host device that is associated with the I/O request, and retrieving a location-based policy that corresponds to the host device, and 
 wherein the given cache slot is allocated based on both the location-based policy and the respective location identifier of the given cache slot. 
 
     
     
       14. The non-transitory computer-readable medium of  claim 13 , wherein allocating the given cache slot based on the respective location identifier of the given cache slot and the location-based policy includes allocating one of the plurality of slots that is situated within a predetermined geographic distance from the computing device. 
     
     
       15. The non-transitory computer-readable medium of  claim 13 , wherein at least one of the plurality of cache slots is resident in a storage controller memory buffer of a solid state drive (SSD). 
     
     
       16. The non-transitory computer-readable medium of  claim 13 , wherein at least one of the plurality of cache slots is part of a persistent memory region of an SSD. 
     
     
       17. The non-transitory computer-readable medium of  claim 13 , wherein:
 the given cache slot is resident in a volatile memory of an SSD, and 
 executing the DMA command includes identifying a parallel computing interface (PCI) address for a portion of the volatile memory of the SSD and using the identified PCI address to execute the DMA command, the PCI address being identified based on the memory address.