Method for forming three-dimensional semiconductor structure and semiconductor structure made thereof

Abstract

This invention relates to a semiconductor structure and a method for forming the semiconductor structure. The method for forming a semiconductor structure includes the following steps: forming a stacking layer on a top surface of a substrate, where the stacking layer includes a plurality of semiconductor layers arranged at intervals in a first direction, and the stacking layer includes a transistor region, a capacitor region, and a bit line region, where the semiconductor layers include semiconductor columns arranged at intervals in a third direction; forming, in the capacitor region, a capacitor extending in the second direction; forming a word line in the transistor region, where the word line extends in the third direction and continuously covers the semiconductor columns arranged at intervals in the third direction; and forming a bit line in the bit line region, where the bit line extends in the first direction.

What is claimed is: 
     
       1. A method for forming a semiconductor structure, comprising:
 forming a stacking layer on a top surface of a substrate, wherein the stacking layer comprises a plurality of semiconductor layers arranged at intervals in a first direction, and the stacking layer comprises a transistor region, two capacitor regions distributed on opposite sides of the transistor region in a second direction, and a bit line region, wherein the stacking layer comprises a plurality of semiconductor columns arranged at intervals in the first direction and a third direction, each semiconductor layer comprises the plurality of semiconductor columns arranged at intervals in the third direction, wherein the first direction is perpendicular to the top surface of the substrate, both of the second direction and the third direction are parallel to the top surface of the substrate, and the second direction intersects the third direction; 
 forming, in each capacitor region, a capacitor extending in the second direction; 
 forming a word line in the transistor region, wherein the word line extends in the third direction and continuously covers the plurality of semiconductor columns arranged at intervals in the third direction; and 
 forming a bit line in the bit line region, wherein the bit line extends in the first direction and is electrically connected to the plurality of semiconductor columns arranged at intervals in the first direction, wherein the stacking layer comprises the plurality of semiconductor layers and a plurality of first sacrificial layers that are alternately stacked in the first direction, wherein each semiconductor column comprises an active column located in the transistor region, and the active column comprises a channel region, and wherein 
 a thickness of each first sacrificial layer in the first direction is four times greater than a width of a gap between two adjacent channel regions in each semiconductor layer in the third direction. 
 
     
     
       2. The method for forming a semiconductor structure according to  claim 1 , wherein the step of forming a stacking layer on a top surface of a substrate comprises:
 alternately depositing the plurality of semiconductor layers and the plurality of first sacrificial layers on the top surface of the substrate in the first direction to form the stacking layer; and 
 etching the stacking layer to form a first trench exposing the substrate, wherein the first trench separates each semiconductor layer into the plurality of semiconductor columns arranged at intervals in the third direction. 
 
     
     
       3. The method for forming a semiconductor structure according to  claim 2 , wherein each semiconductor column comprises a conductive column located in each capacitor region, and the step of forming, in each capacitor region, a capacitor extending in the second direction comprises:
 removing the first sacrificial layer in each capacitor region to form a first gap between two adjacent semiconductor layers in each capacitor region; 
 forming, in the first gap, a conductive layer covering the conductive column, a dielectric layer covering the conductive layer, an upper electrode layer covering the dielectric layer, and a common electrode layer covering the upper electrode layer; and 
 forming a capacitor comprising the conductive column, the conductive layer, the dielectric layer, the upper electrode layer, and the common electrode layer. 
 
     
     
       4. The method for forming a semiconductor structure according to  claim 3 , wherein the step of forming a capacitor comprising the conductive column, the conductive layer, the dielectric layer, the upper electrode layer, and the common electrode layer comprises:
 forming a conductive layer that continuously covers inner walls of the first gaps arranged at intervals in the first direction; 
 forming a dielectric layer covering a surface of the conductive layer; 
 forming an upper electrode layer covering a surface of the dielectric layer; 
 forming a common electrode layer covering a surface of the upper electrode layer; 
 removing the conductive layer, the dielectric layer, the upper electrode layer, and the common electrode layer that cover a sidewall of the first sacrificial layer in the transistor region; and 
 forming a first opening between two adjacent semiconductor layers in each capacitor region, wherein the conductive column, and the conductive layer, the dielectric layer, the upper electrode layer, and the common electrode layer that remain in the first gap form the capacitor. 
 
     
     
       5. The method for forming a semiconductor structure according to  claim 4 , wherein each semiconductor column comprises an active column located in the transistor region, the active column comprises a channel region, and a source region and a drain region distributed on opposite sides of the channel region in the second direction, the drain region is adjacent to each capacitor region, the source region is adjacent to the bit line region, and wherein the step of forming a word line in the transistor region comprises:
 removing the first sacrificial layer in the transistor region and the stacking layer in the bit line region; 
 forming a second gap exposing at least the channel region in the transistor region and a second trench exposing the substrate in the bit line region; and 
 forming, in the second gap, the word line that extends in the third direction and continuously covers the channel regions arranged at intervals in the third direction. 
 
     
     
       6. The method for forming a semiconductor structure according to  claim 5 , wherein the step of forming a second gap exposing at least the channel region in the transistor region and a second trench exposing the substrate in the bit line region comprises:
 forming a capacitor isolation layer filling the first opening; 
 removing the stacking layer in the bit line region to form the second trench exposing the substrate in the bit line region; and 
 removing the first sacrificial layer in the transistor region along the second trench to form, between two adjacent semiconductor layers in the transistor region, the second gap exposing the channel region, the drain region, and the source region. 
 
     
     
       7. The method for forming a semiconductor structure according to  claim 5 , wherein a bottom of the second trench exposes the top surface of the substrate; or
 the second trench extends to an inside of the substrate. 
 
     
     
       8. The method for forming a semiconductor structure according to  claim 6 , wherein the stacking layer comprises two transistor subregions distributed on opposite sides of the bit line region in the second direction, and one capacitor subregion is located on a side of the transistor region that is away from the bit line region, and wherein the step of removing the first sacrificial layer in the transistor region along the second trench comprises:
 simultaneously removing the first sacrificial layers in the two transistor subregions along the second trench. 
 
     
     
       9. The method for forming a semiconductor structure according to  claim 6 , wherein the step of forming, in the second gap, the word line that extends in the third direction and continuously covers the channel regions arranged at intervals in the third direction comprises:
 forming an initial word line layer that covers an inner wall of the second gap and an inner wall of the second trench, wherein the initial word line layer continuously covers at least the active columns arranged at intervals in the third direction; 
 forming an isolation layer that covers a surface of the initial word line layer and fills the second gap and the second trench; and 
 removing the initial word line layer and the isolation layer that are located in the second trench and above the source region and the drain region, to form a second opening between two adjacent drain regions and a third opening between two adjacent source regions, wherein the initial word line layer remaining above the channel region is configured as the word line, and the isolation layer remaining between two adjacent word lines is configured as a word line isolation layer. 
 
     
     
       10. The method for forming a semiconductor structure according to  claim 9 , wherein the step of forming an initial word line layer that covers an inner wall of the second gap and an inner wall of the second trench comprises:
 forming, by using a lateral atomic layer deposition process, the initial word line layer that covers the inner wall of the second gap and the inner wall of the second trench. 
 
     
     
       11. The method for forming a semiconductor structure according to  claim 9 , before forming the bit line in the bit line region, further comprising:
 removing the capacitor isolation layer; 
 forming a dielectric layer that fills the first opening, the second opening, the third opening, and the second trench; and 
 removing the dielectric layer in the second trench. 
 
     
     
       12. The method for forming a semiconductor structure according to  claim 6 , wherein the step of forming, in the second gap, the word line that extends in the third direction and continuously covers the channel regions arranged at intervals in the third direction comprises:
 depositing a gate material on an inner wall of the second gap and an inner wall of the second trench along the second trench to form an initial gate layer that covers the active column, wherein two adjacent initial gate layers in the third direction are independent of each other; 
 depositing an initial word line material along the second trench to form an initial word line layer that covers a surface of the initial gate layer, wherein the initial word line layer continuously covers at least the active columns arranged at intervals in the third direction; 
 forming an isolation layer that covers a surface of the initial word line layer and fills the second gap and the second trench; and 
 removing the initial gate layer, the initial word line layer, and the isolation layer that are located in the second trench and above the source region and the drain region, to form a second opening between two adjacent drain regions and a third opening between two adjacent source regions, wherein the initial gate layer remaining above the channel region is configured as a gate layer, the initial word line layer remaining above the gate layer and between two adjacent gate layers in the third direction is configured as the word line, and the isolation layer remaining between two adjacent word lines is configured as a word line isolation layer. 
 
     
     
       13. The method for forming a semiconductor structure according to  claim 1 , wherein a material of the semiconductor layer is a silicon material doped with ions. 
     
     
       14. The method for forming a semiconductor structure according to  claim 1 , wherein the semiconductor structure is a dynamic random access memory. 
     
     
       15. A semiconductor structure, wherein the semiconductor structure is formed by using the method according to  claim 1 . 
     
     
       16. The semiconductor structure according to  claim 15 , wherein the semiconductor structure is a dynamic random access memory.