Gallium nitride-on-silicon devices

Abstract

A gallium nitride-on-silicon structure is disclosed in which the two-dimensional electron gas (2DEG) layer is a discontinuous layer that includes at least two 2DEG segments. Each 2DEG segment is separated from another 2DEG segment by a gap. The 2DEG layer can be depleted by a p-doped gallium nitride layer that is disposed over a portion of an aluminum gallium nitride layer. Additionally or alternatively, a trench may be formed in the structure through the 2DEG layer to produce a gap in the 2DEG layer. An electrical component is positioned over at least a portion of a gap.

What is claimed is: 
     
       1. An electronic device, comprising:
 a first electrical component; 
 an electrical component device comprising:
 a buffer layer disposed over a frontside surface of a substrate; 
 a first layer of gallium nitride disposed over the buffer layer; 
 a second layer of aluminum gallium nitride disposed over the first layer, wherein a two-dimensional electron gas (2DEG) layer is disposed at an interface between the first layer and the second layer, and the second layer comprises a first 2DEG segment and a second 2DEG segment and a gap between the first and the second 2DEG segments; 
 a second electrical component positioned over the second layer and over at least a portion of the gap between the first and the second 2DEG segments, wherein the second electrical component is operably connected to the first electrical component; and 
 
 a third layer of p-doped gallium nitride disposed over only a portion of the second layer, wherein the gap between the first 2DEG segment and the second 2DEG segment corresponds to a contour of the p-doped gallium nitride layer. 
 
     
     
       2. The electronic device of  claim 1 , further comprising a trench formed from a backside surface of the substrate through the substrate, through the buffer layer, through the first layer, and through the 2DEG layer, wherein the trench creates the gap in the 2DEG layer. 
     
     
       3. The electronic device of  claim 1 , wherein the substrate is a silicon-based substrate. 
     
     
       4. The electronic device of  claim 2 , further comprising a dielectric material in the trench. 
     
     
       5. The electronic device of  claim 1 , wherein:
 the first layer of gallium nitride is a first layer of gallium nitride (GayN1-y); and 
 the buffer layer is a layer of gallium nitride (GaxN1-x). 
 
     
     
       6. The electronic device of  claim 1 , wherein the buffer layer is configured to gradually transfer a crystal lattice from the substrate to the buffer layer for lattice matching. 
     
     
       7. The electronic device of  claim 1 , wherein the electronic device is a printed circuit board. 
     
     
       8. The electronic device of  claim 1 , wherein the electronic device is a monolithic microwave integrated circuit or a microwave integrated circuit. 
     
     
       9. The electronic device of  claim 1 , wherein the first electrical component comprises an inductor. 
     
     
       10. An electrical component device, comprising:
 a buffer layer disposed over a high resistivity substrate; 
 a first layer of gallium nitride disposed over the buffer layer; 
 a second layer of aluminum gallium nitride disposed over the first layer, wherein a layer of a two-dimensional electron gas (2DEG) formed at an interface between the first layer and the second layer comprises a first 2DEG segment and a second 2DEG segment and a gap between the first and the second 2DEG segments; and 
 an electrical component positioned over the second layer and over at least a portion of the gap between the first and the second 2DEG segments. 
 
     
     
       11. The electrical component device of  claim 10 , further comprising a third layer of p-doped gallium nitride disposed over only a portion of the second layer, wherein the gap between the first 2DEG segment and the second 2DEG segment corresponds to a contour of the p-doped gallium nitride layer. 
     
     
       12. The electrical component device of  claim 11 , wherein the electrical component comprises an inductor positioned over the third layer overlying the second layer. 
     
     
       13. The electrical component device of  claim 10 , further comprising a trench formed from a backside through the substrate, the buffer layer, the first layer, and the layer of 2DEG, wherein the gap between the first and the second 2DEG segments is the trench. 
     
     
       14. The electrical component device of  claim 10 , further comprising a trench formed from the frontside through the second layer and the layer of 2DEG, wherein the gap between the first and the second 2DEG segments is the trench. 
     
     
       15. The electrical component device of  claim 10 , wherein the electrical component comprises an inductor. 
     
     
       16. A method of fabricating an electrical component device, comprising:
 forming a buffer layer over a substrate; 
 forming a first layer of gallium nitride over the buffer layer; 
 forming a second layer of aluminum gallium nitride over the first layer; 
 forming a first two dimensional electron gas (2DEG) segment and a second 2DEG segment at an interface between the first layer and the second layer including forming a third layer of a p-doped gallium nitride over a portion of the second layer, wherein the first 2DEG segment is separated from the second 2DEG segment by a gap that corresponds to a contour of the third layer; 
 disposing an electrical component over the second layer, over the third layer and over at least a portion of the gap; and 
 patterning the third layer to form one or more openings in the third layer prior to disposing the electrical component over the third layer, wherein an additional 2DEG segment is formed at the interface between the first layer and the second layer below each of the one or more openings in the third layer. 
 
     
     
       17. The method of  claim 16 , wherein the electrical component is an inductor. 
     
     
       18. The method of  claim 16 , wherein the substrate is a silicon-based substrate. 
     
     
       19. The method of  claim 16 , wherein forming the first 2DEG segment and the second 2DEG segment comprises:
 forming a trench through the 2DEG layer to produce the first 2DEG segment and the second 2DEG segment, wherein the trench comprises the gap; and 
 forming a dielectric material in the trench. 
 
     
     
       20. The method of  claim 16 , wherein the substrate comprises a high resistivity substrate.