Reconfigurable PUF with two PUF functions

Abstract

A reconfigurable PUF with two PUF functions comprises 2 m ×n PUF cells, a sequential control module, a row selection module, n amplification modules, n first bit lines, and n second bit lines. Each of the 2 m ×n PUF cells comprises a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor and a seventh NMOS transistor. The PUF cells can provide two independent responses, and can operate in a SRAM mode and an inverter mode. Therefore, the reconfigurable PUF with two PUF functions can operate both in the SRAM mode and the inverter mode, and a PUF operating mode with higher reliability is selected for generating final responses.

What is claimed is: 
     
       1. A reconfigurable physically unclonable function (PUF) with two PUF functions, comprising 2 m ×n PUF cells, a sequential control circuit, a row selection circuit, n amplification circuits, n first bit lines, and n second bit lines, wherein m is an integer greater than or equal to 1, n is an integer greater than or equal to 1,
 wherein the row selection circuit has an enable terminal, m output terminals, 2 m  first output terminals and 2 m  second output terminals, m bits of row selection signals are input to the m input terminals of the row selection circuit, the row selection circuit is configured to convert the m bits of row selection signals into 2 m  bits of row address signals and 2 m  bits of row initialization signals, configured to output the 2 m  bits of row address signals via the 2 m  first output terminals of the row selection circuit, and configured to output the 2 m  bits of row initialization signals via the 2 m  second output terminals of the row selection circuit, the 2 m  bits of row address signals and the 2 m  bits of row initialization signals are all binary data, only one bit of data in the 2 m  bits of row address signals is 1, the other bits of data of the 2 m  bits of row address signals are all 0, only one bit of data of the 2 m  bits of row initialization signals is 0, the other bits of data of the 2 m  bits of row initialization signals are all 1, the k th  bit of data of the 2 m  bits of row address signals is output via the k th  first output terminal of the row selection circuit, the k th  bit of data of the 2 m  bits of row initialization signals is output via the k th  second output terminal of the row selection circuit, the k th  bit of data of the 2 m  bits of row address signals is different from the k th  bit of data of the 2 m  bits of row initialization signals, and k=1, 2, . . . , 2 m ; 
 wherein each of the n amplification circuits has an enable terminal, a first input terminal, a second input terminal and an output terminal; 
 wherein the sequential control circuit has a first control terminal and a second control terminal, and is configured to generate two paths of enable signals for controlling sequential matching of the row selection circuit and the n amplification circuits, wherein a first path of an enable signal is output via the first control terminal of the sequential control circuit, and a second path of an enable signal is output via the second control terminal of the sequential control circuit; 
 wherein the 2 m ×n PUF cells are distributed in 2 m  rows and n columns to form a PUF array; each PUF cell has a power terminal, a first input terminal, a second input terminal, a third input terminal, a first output terminal and a second output terminal; the first control terminal of the sequential control circuit is connected to the enable terminal of the row selection module, the second control terminal of the sequential control circuit is connected to the enable terminals of the n amplification circuits, the k th  first output terminal of the row selection circuit is connected to the first input terminals of the n PUF cells in the k th  row of the PUF array, the k th  second output terminal of the row selection circuit is connected to the second input terminals of the n PUF cells in the k th  row of the PUF array, the first output terminals of the 2 m  PUF cells in the j th  column of the PUF array are all connected to the j th  first bit line, the j th  first bit line is connected to the first input terminal of the j th  amplification circuit, the second output terminals of the 2 m  PUF cells in the j th  column of the PUF array are all connected to the j th  second bit line, the j th  second bit line is connected to the second input terminal of the j th  amplification circuit, and j=1, 2, . . . , n; 
 wherein when data input to the first input terminals of the n PUF cells in one row of the PUF array is 1 and data input to the second input terminals of the n PUF cells in said row of the PUF array is 0, the n PUF cells enter an operating state, the first output terminal and the second output terminal of each PUF cell in said row respectively generate and output voltage signals, all the PUF cells in the other rows enter a dormant state, and the first output terminals and the second output terminals of the PUF cells in the other rows do not output voltage signals; each PUF cell comprises a first P-channel metal-oxide-semiconductor (PMOS) transistor, a second PMOS transistor, a first N-channel Metal Oxide Semiconductor (NMOS) transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor and a seventh NMOS transistor, wherein a source of the first PMOS transistor and a source of the second PMOS transistor are connected and a connecting terminal thereof is the power terminal of the PUF cell, a gate of the first PMOS transistor, a drain of the second PMOS transistor, a drain of the sixth NMOS transistor, a source of the fourth NMOS transistor, a gate of the second NMOS transistor, a drain of the first NMOS transistor and a drain of the third NMOS transistor are connected, a drain of the first PMOS transistor, a gate of the second PMOS transistor, a source of the fifth NMOS transistor, a drain of the second NMOS transistor, a drain of the seventh NMOS transistor, a drain of the fourth NMOS transistor and a gate of the third NMOS transistor are connected, a gate of the first NMOS transistor and a gate of the seventh NMOS transistor are connected and a connecting terminal thereof is the second input terminal of the PUF cell, a source of the first NMOS transistor, a source of the third NMOS transistor, a source of the second NMOS transistor and a source of the seventh NMOS transistor are all grounded, a gate of the fourth NMOS transistor is the third input terminal of the PUF cell, a gate of the fifth NMOS transistor and a gate of the sixth NMOS transistor are connected and a connecting terminal thereof is the first input terminal of the PUF cell, a drain of the fifth NMOS transistor is the first output terminal of the PUF cell, and a source of the sixth NMOS transistor is the second output terminal of the PUF cell; 
 wherein the reconfigurable PUF with two PUF functions further comprises a bit configuration circuit and a biasing circuit, wherein the bit configuration circuit has n output terminals, the j th  output terminal of the bit configuration circuit is connected to the third input terminals of the 2 m  PUF cells in the j th  column of the PUF cell, the bit configuration circuit is configured to generate n bits of binary configuration signals, and the j th  bit of the n bits of binary configuration signals is output via the j th  output terminal of the bit configuration circuit; 
 wherein when the j th  bit of the n bits of binary configuration signals is 1, the 2 m  PUF cells in the j th  column of the PUF cell are configured to be in an inverter mode; 
 wherein when the j th  bit of the n bits of binary configuration signals is 0, the 2 m  PUF cells in the j th  column of the PUF cells are configured to be in a SRAM mode; 
 wherein the biasing circuit has n output terminals, the j th  output terminal of the biasing circuit is connected to the power terminals of the 2 m  PUF cells in the j th  column of the PUF cell, the biasing circuit is configured to generate n paths of bias voltages, wherein the n th  path of bias voltage is output via the j th  output terminal of the biasing circuit; 
 wherein when one PUF cell enters the operating state and is in the SRAM mode, a large voltage deviation is generated due to the cross-coupled inverters competition between the first bit line and the second bit line which are connected to the first output terminal and the second output terminal of said PUF cell, wherein the first bit line theoretically generates a voltage equal to a bias voltage input to the power terminal of said PUF cell and the second bit line theoretically generate a voltage 0; 
 wherein due to presence of a process variation during circuit fabrication, a voltage generated by the first bit line is close to the bias voltage, a voltage generated by the second bit line is close to 0, and in this case, the output terminal of each of the n amplification circuits connected to the first bit line and the second bit line outputs 1; 
 wherein when one PUF cell enters the operating state and is in the inverter mode, the first bit line and the second bit line which are connected to the first output terminal and the second output terminal of said PUF cell respectively generate a voltage equal to half of the bias voltage input to the power terminal of the PUF cell; 
 wherein due to presence of a process variation during circuit fabrication, a voltage generated by the first bit line is close to half of the bias voltage, a voltage generated by the second bit line is close to half of the bias voltage, and the voltage generated by the first bit line is not equal to the voltage generated by the second bit line; in this case, when the voltage generated by the first bit line is greater than half of the bias voltage, the output terminal of each of the n amplification circuits connected to the first bit line and the second bit line outputs 1; when the voltage generated by the first bit line is less than half of the bias voltage, the output terminal of each of the n amplification circuits connected to the first bit line and the second bit line outputs 0; 
 wherein in the PUF array, instable PUF cells are in the inverter mode after entering the operating state, and stable PUF cells are in the SRAM mode after entering the operating state. 
 
     
     
       2. The reconfigurable PUF with the two PUF functions according to  claim 1 , wherein the row selection circuit is realized by a decoder. 
     
     
       3. The reconfigurable PUF with the two PUF functions according to  claim 1 , wherein each of the n amplification circuits comprises a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, a tenth PMOS transistor, an eleventh PMOS transistor, a twelfth PMOS transistor, a thirteenth PMOS transistor, a fourteenth PMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, a twelfth NMOS transistor, a thirteenth NMOS transistor, a fourteenth NMOS transistor and a fifteenth NMOS transistor;
 wherein a positive supply voltage is accessed to a source of the third PMOS transistor, a source of the sixth PMOS transistor, a source of the ninth PMOS transistor and a source of the twelfth PMOS transistor, a gate of the third PMOS transistor, a gate of the sixth PMOS transistor, a gate of the ninth PMOS transistor and a gate of the twelfth PMOS transistor are connected and a connecting terminal thereof is the enable terminal of each of the n amplification circuits, a drain of the third PMOS transistor and a source of the fourth PMOS transistor are connected, a drain of the sixth PMOS transistor and a source of the seventh PMOS transistor are connected, a drain of the fourth PMOS transistor and a source of the fifth PMOS transistor are connected, a drain of the seventh PMOS transistor and a source of the eighth PMOS transistor are connected, a gate of the fourth PMOS transistor, a gate of the fifth PMOS transistor, a gate of the eighth NMOS transistor and a gate of the ninth NMOS transistor are connected and a connecting terminal thereof is the first input terminal of each of the n amplification circuits, a drain of the fifth PMOS transistor, a drain of the eight NMOS transistor, a gate of the seventh PMOS transistor, a gate of the eighth PMOS transistor, a gate of the tenth NMOS transistor and a gate of the eleventh NMOS transistor are connected, a drain of the eighth PMOS transistor and a drain of the tenth NMOS transistor are connected and a connecting terminal thereof is the output terminal of each of the n amplification circuits, a source of the eighth NMOS transistor and a drain of the ninth NMOS transistor are connected, a source of the ninth NMOS transistor is grounded, a source of the tenth NMOS transistor and a drain of the eleventh NMOS transistor are connected, and a source of the eleventh NMOS transistor is grounded; a drain of the ninth PMOS transistor and a source of the tenth PMOS transistor are connected, a drain of the twelfth PMOS transistor and a source of the thirteenth PMOS transistor are connected, a drain of the tenth PMOS transistor and a source of the eleventh PMOS transistor are connected, a drain of the thirteenth PMOS transistor and a source of the fourteenth PMOS transistor are connected, a gate of the tenth PMOS transistor, a gate of the eleventh PMOS transistor, a gate of the twelfth NMOS transistor and a gate of the thirteenth NMOS transistor are connected and a connecting terminal thereof is the second input terminal of each of the n amplification circuits, a drain of the eleventh PMOS transistor, a drain of the twelfth NMOS transistor, a gate of the thirteenth PMOS transistor, a gate of the fourteenth PMOS transistor, a gate of the fourteenth NMOS transistor and a gate of the fifteenth NMOS transistor are connected, a drain of the fourteenth PMOS transistor and a drain of the fourteenth NMOS transistor are connected, a source of the twelfth NMOS transistor and a drain of the thirteenth NMOS transistor are connected, a source of the thirteenth NMOS transistor is grounded, a source of the fourteenth NMOS transistor and a drain of the fifth NMOS transistor are connected, and a source of the fifteenth NMOS transistor is grounded, 
 wherein in each of the n amplification circuits, the third PNMOS transistor, the fourth PMOS transistor, the fifth PMOS transistor, the sixth PMOS transistor, the seventh PMOS transistor, the eighth PMOS transistor, the eighth NMOS transistor, the ninth NMOS transistor, the tenth NMOS transistor and the eleventh NMOS transistor form a first amplifier, and the ninth PMOS transistor, the tenth PMOS transistor, the eleventh PMOS transistor, the twelfth PMOS transistor, the thirteenth PMOS transistor, the fourteenth PMOS transistor, the twelfth NMOS, the thirteenth NMOS transistor, the fourteenth NMOS transistor and the fifth NMOS transistor form a second amplifier; 
 wherein the second amplifier guarantees a fair competition of the PUF cell, and the first amplifier and the second amplifier identical with the first amplifier guarantee the randomness of the PUF cell; 
 wherein when the second path of the enable signal which is output by the sequential control circuit is 1, the third PMOS transistor, the sixth PMOS transistor, the ninth PMOS transistor and the twelfth PMOS transistor are turned off, the eighth NMOS transistor, the ninth NMOS transistor, the tenth NMOS transistor, the eleventh NMOS transistor, the twelfth NMOS transistor, the thirteenth NMOS transistor, the fourteenth NMOS transistor and the fifth NMOS transistor leak a current, each of the n amplification circuits does not operate, and the output terminal of each of the n amplification circuits output 0; 
 wherein when the second path of the enable signal which is output by the sequential control circuit is 0, the third PMOS transistor, the sixth PMOS transistor, the ninth PMOS transistor and the twelfth PMOS transistor are turned on, and each of the n amplification circuits enters the operating state; 
 wherein when a voltage accessed to the first input terminal of each of the n amplification circuits is greater than half of the bias voltage accessed to the power terminal of the PUF cell connected to each of the n amplification circuits, the fourth PMOS transistor, the fifth PMOS transistor, the tenth PMOS transistor and the eleventh PMOS transistor are turned off, and the output terminal of each of the n amplification circuits outputs 1; 
 wherein when the voltage accessed to the first input terminal of each of the n amplification circuits is less than half of the bias voltage accessed to the power terminal of the PUF cell connected to each of the n amplification circuits, the eighth NMOS transistor, the ninth NMOS transistor, the seventh PMOS transistor and the eighth PMOS transistor are turned off, and the output terminal of each of the n amplification circuits outputs 0; 
 wherein when a voltage accessed to the second input terminal of each of the n amplification circuits is greater than half of the bias voltage accessed to the power terminal of the PUF cell connected to each of the n amplification circuits, the tenth PMOS transistor, the eleventh PMOS transistor, the fourteenth NMOS transistor and the fifth NMOS transistor are turned off, an output of the output terminal of each of the n amplification circuits has no influence; and 
 wherein when the voltage accessed to the second input terminal of each of the n amplification circuits is less than half of the bias voltage accessed to the power terminal of the PUF cell connected to each of the n amplification circuits, the twelfth NMOS transistor, the thirteenth PMOS transistor, and the fourteenth PMOS transistor are turned off, and an output of the output terminal of each of the n amplification circuits has no influence.