Processing pipeline with zero loop overhead

Abstract

Techniques are disclosed for reducing or eliminating loop overhead caused by function calls in processors that form part of a pipeline architecture. The processors in the pipeline process data blocks in an iterative fashion, with each processor in the pipeline completing one of several iterations associated with a processing loop for a commonly-executed function. The described techniques leverage the use of message passing for pipelined processors to enable an upstream processor to signal to a downstream processor when processing has been completed, and thus a data block is ready for further processing in accordance with the next loop processing iteration. The described techniques facilitate a zero loop overhead architecture, enable continuous data block processing, and allow the processing pipeline to function indefinitely within the main body of the processing loop associated with the commonly-executed function where efficiency is greatest.

What is claimed is: 
     
       1. A processing pipeline, comprising:
 a first processor associated with a first memory; and 
 a second processor associated with a second memory, the second processor being operably coupled to the first processor via a data interface and being downstream from the first processor in the processing pipeline, 
 wherein the first processor and the second processor are capable of processing data blocks in accordance with a plurality of data processing loop iterations associated with a commonly-executed function, 
 wherein the first processor is capable of processing a data block in accordance with a first one of the plurality of data processing loop iterations to provide a processed data block, and storing the processed data block in the first memory, 
 wherein the second processor receives the processed data block based upon the processed data block being stored in the first memory, 
 wherein the second processor is capable of processing the processed data block in accordance with a second one of the plurality of data processing loop iterations and storing a result of processing the processed data block in the second memory, 
 wherein the first processor and the second processor are each capable of processing the data block and the processed data block, respectively, as part of a continuous execution of the first and the second ones of the plurality of data processing loop iterations associated with the commonly-executed function, 
 wherein the processing pipeline is part of a vector processing pipeline architecture, and 
 wherein the commonly-executed function is implemented to perform a calculation of filter coefficients. 
 
     
     
       2. The processing pipeline of  claim 1 , wherein the second processor is capable of receiving the processed data block from the first processor via the data interface while the first processor processes another data block in accordance with a third one of the plurality of data processing loop iterations. 
     
     
       3. The processing pipeline of  claim 1 , wherein the first processor is capable of processing the data block in accordance with the first one of the plurality of data processing loop iterations with zero loop overhead, and
 wherein the second processor is capable of processing the processed data block in accordance with the second one of the plurality of data processing loop iterations with zero loop overhead. 
 
     
     
       4. The processing pipeline of  claim 1 , wherein the first processor and the second processor are each capable of processing respective data blocks in accordance with the plurality of data processing loop iterations without exiting a loop body associated with the commonly-executed function. 
     
     
       5. The processing pipeline of  claim 1 , wherein the second processor is capable of receiving the processed data block via the data interface by receiving the processed data block via the first memory of the first processor. 
     
     
       6. The processing pipeline of  claim 1 , wherein the data interface includes a first-in-first-out (FIFO) buffer. 
     
     
       7. The processing pipeline of  claim 1 , wherein the second processor is capable of processing the processed data block concurrently with the first processor processing another data block in accordance with a third one of the plurality of data processing loop iterations. 
     
     
       8. The processing pipeline of  claim 2 , wherein the data interface comprises a buffer, and
 wherein the first processor and the second processor are capable of using the buffer to process the data blocks, which are received in a streaming manner. 
 
     
     
       9. The processing pipeline of  claim 1 , further comprising:
 a further data interface capable of receiving the data block that is processed by the first processor as part of a data stream. 
 
     
     
       10. The processing pipeline of  claim 9 , wherein the further data interface is capable of receiving data blocks via the data stream in accordance with a predetermined rate. 
     
     
       11. A processing pipeline, comprising:
 a data interface; and 
 a plurality of processors operably connected to one another and capable of processing data blocks in accordance with a plurality of data processing loop iterations associated with a commonly-executed function, the plurality of processors including a producer processor and a consumer processor, the producer processor being capable of providing, via the data interface, data to the consumer processor that is downstream from the producer processor with respect to the processing pipeline, 
 wherein the producer processor is capable of processing a data block in accordance with a first one of the plurality of data processing loop iterations to provide a processed data block, and storing the processed data block in a first memory, 
 wherein the consumer processor receives the processed data block based upon the processed data block being stored in the first memory, 
 wherein the consumer processor is capable of processing the processed data block in accordance with a second one of the plurality of data processing loop iterations and storing a result of processing the processed data block in a second memory, 
 wherein the producer processor and the consumer processor are each capable of processing the data block and the processed data block, respectively, as part of a continuous execution of the first and the second ones of the plurality of data processing loop iterations associated with the commonly-executed function, 
 wherein the processing pipeline is part of a vector processing pipeline architecture, and 
 wherein the commonly-executed function is implemented to perform a calculation of filter coefficients. 
 
     
     
       12. The processing pipeline of  claim 11 , wherein the consumer processor is capable of receiving the processed data block from the producer processor via the data interface while the producer processor processes another data block in accordance with a third one of the plurality of data processing loop iterations. 
     
     
       13. The processing pipeline of  claim 11 , wherein the producer processor is capable of processing the data block in accordance with the first one of the plurality of data processing loop iterations with zero loop overhead, and
 wherein the consumer processor is capable of processing the processed data block in accordance with the second one of the plurality of data processing loop iterations with zero loop overhead. 
 
     
     
       14. The processing pipeline of  claim 11 , wherein the producer processor and the consumer processor are each capable of processing respective data blocks in accordance with the plurality of data processing loop iterations without exiting a loop body associated with the commonly-executed function. 
     
     
       15. The processing pipeline of  claim 11 , wherein the consumer processor is capable of receiving the processed data block via the data interface by receiving the processed data block via the first memory of the producer processor. 
     
     
       16. The processing pipeline of  claim 11 , wherein the data interface includes a first-in-first-out (FIFO) buffer. 
     
     
       17. The processing pipeline of  claim 11 , wherein the consumer processor is capable of processing the processed data block concurrently with the producer processor processing another data block in accordance with a third one of the plurality of data processing loop iterations. 
     
     
       18. The processing pipeline of  claim 11 , wherein the data interface comprises a buffer, and
 wherein the producer processor and the consumer processor are capable of using the buffer to process the data blocks, which are received in a streaming manner. 
 
     
     
       19. The processing pipeline of  claim 11 , further comprising:
 a further data interface capable of receiving the data block that is processed by the producer processor as part of a data stream. 
 
     
     
       20. The processing pipeline of  claim 19 , wherein the further data interface is capable of receiving data blocks via the data stream in accordance with a predetermined rate. 
     
     
       21. A processing pipeline, comprising:
 an upstream processor associated with a first memory; and 
 a downstream processor associated with a second memory, the upstream processor and the downstream processor each being operably connected to a data interface; 
 wherein the upstream processor and the downstream processor are capable of processing data blocks in accordance with a plurality of data processing loop iterations associated with a commonly-executed function, 
 wherein the upstream processor is capable of processing a data block in accordance with a first one of the plurality of data processing loop iterations to provide a processed data block, and storing the processed data block in the first memory, 
 wherein the downstream processor receives the processed data block based upon the processing of the data block by the upstream processor being completed, 
 wherein the downstream processor is capable of processing the processed data block in accordance with a second one of the plurality of data processing loop iterations and storing a result of processing the processed data block in the second memory, 
 wherein the upstream processor and the downstream processor are each capable of processing the data block and the processed data block, respectively, as part of continuous execution of the first and the second ones of the plurality of data processing loop iterations associated with the commonly-executed function, 
 wherein the processing pipeline is part of a vector processing pipeline architecture, and 
 wherein the commonly-executed function is implemented to perform a calculation of filter coefficients. 
 
     
     
       22. The processing pipeline of  claim 21 , wherein the downstream processor is capable of receiving the processed data block from the upstream processor via the data interface while the upstream processor processes another data block in accordance with a third one of the plurality of data processing loop iterations. 
     
     
       23. The processing pipeline of  claim 21 , wherein the upstream processor is capable of processing the data block in accordance with the first one of the plurality of data processing loop iterations with zero loop overhead, and
 wherein the downstream processor is capable of processing the processed data block in accordance with the second one of the plurality of data processing loop iterations with zero loop overhead. 
 
     
     
       24. The processing pipeline of  claim 21 , wherein the upstream processor and the downstream processor are each capable of processing respective data blocks in accordance with the plurality of data processing loop iterations without exiting a loop body associated with the commonly-executed function. 
     
     
       25. The processing pipeline of  claim 21 , wherein the downstream processor is capable of receiving the processed data block via the data interface by receiving the processed data block via the first memory of the upstream processor. 
     
     
       26. The processing pipeline of  claim 21 , wherein the data interface includes a first-in-first-out (FIFO) buffer. 
     
     
       27. The processing pipeline of  claim 21 , wherein the downstream processor is capable of processing the processed data block concurrently with the upstream processor processing another data block in accordance with a third one of the plurality of data processing loop iterations. 
     
     
       28. The processing pipeline of  claim 21 , wherein the data interface comprises a buffer, and
 wherein the upstream processor and the downstream processor are capable of using the buffer to process the data blocks, which are received in a streaming manner. 
 
     
     
       29. The processing pipeline of  claim 21 , further comprising:
 a further data interface capable of receiving the data block that is processed by the upstream processor as part of a data stream. 
 
     
     
       30. The processing pipeline of  claim 29 , wherein the further data interface is capable of receiving data blocks via the data stream in accordance with a predetermined rate. 
     
     
       31. A system, comprising:
 a first data interface capable of receiving data blocks from a data source as part of a data stream; and 
 a processing pipeline comprising:
 a second data interface; 
 a first processor associated with a first memory; and 
 a second processor associated with a second memory, the second processor being operably coupled to the first processor via the second data interface and being downstream from the first processor in the processing pipeline, 
 wherein the first processor and the second processor are capable of processing data blocks received via the first data interface in accordance with a plurality of data processing loop iterations associated with a commonly-executed function, 
 wherein the first processor is capable of processing a data block in accordance with a first one of the plurality of data processing loop iterations to provide a processed data block, and storing the processed data block in the first memory, 
 wherein the second processor receives the processed data block based upon the processed data block being stored in the first memory, 
 wherein the second processor is capable of processing the processed data block in accordance with a second one of the plurality of data processing loop iterations and storing a result of processing the processed data block in the second memory, 
 wherein the first processor and the second processor are each capable of processing the data block and the processed data block, respectively, as part of a continuous execution of the first and the second ones of the plurality of data processing loop iterations associated with the commonly-executed function, 
 wherein the processing pipeline is part of a vector processing pipeline architecture, and 
 wherein the commonly-executed function is implemented to perform a calculation of filter coefficients. 
 
 
     
     
       32. The system of  claim 31 , wherein the second processor is capable of receiving the processed data block from the first processor via the second data interface while the first processor processes another data block in accordance with a third one of the plurality of data processing loop iterations. 
     
     
       33. The system of  claim 31 , wherein the first processor is capable of processing the data block in accordance with the first one of the plurality of data processing loop iterations with zero loop overhead, and
 wherein the second processor is capable of processing the processed data block in accordance with the second one of the plurality of data processing loop iterations with zero loop overhead. 
 
     
     
       34. The system of  claim 31 , wherein the first processor and the second processor are each capable of processing respective data blocks in accordance with the plurality of data processing loop iterations without exiting a loop body associated with the commonly-executed function. 
     
     
       35. The system of  claim 31 , wherein the second processor is capable of receiving the processed data block via the second data interface by receiving the processed data block via the first memory of the first processor. 
     
     
       36. The system of  claim 31 , wherein the second data interface includes a first-in-first-out (FIFO) buffer. 
     
     
       37. The system of  claim 31 , wherein the second processor is capable of processing the processed data block concurrently with the first processor processing another data block in accordance with a third one of the plurality of data processing loop iterations. 
     
     
       38. The system of  claim 31 , wherein the second data interface comprises a buffer, and
 wherein the first processor and the second processor are capable of using the buffer to process the data blocks, which are received in a streaming manner. 
 
     
     
       39. The system of  claim 31 , wherein the first data interface is capable of receiving the data blocks via the data stream in accordance with a predetermined rate.