Display panel with storage capacitor having different carrier mobility regions and display device

Abstract

A display panel and a display device, the display panel includes a sub-pixel, wherein the sub-pixel includes a pixel circuit and a light emitting element, the pixel circuit includes a data writing sub-circuit, a storage sub-circuit and a driving sub-circuit. The storage sub-circuit includes a storage capacitor (Cst) including a first capacitor electrode and a second capacitor electrode, the second capacitor electrode includes a first region, a second region and a third region, a carrier mobility in the second region is different from a carrier mobility in the first and third regions, and an area of the second region is larger than an area of the first and third regions. The control electrode of the driving sub-circuit and the first capacitor electrode are disposed in the same layer and implemented as an integral structure.

What is claimed is: 
     
         1 . A display panel, comprising:
 a base substrate and a sub-pixel on the base substrate, wherein the sub-pixel comprises a pixel circuit and a light emitting element, the pixel circuit comprises a data writing sub-circuit, a storage sub-circuit and a driving sub-circuit;   wherein the data writing sub-circuit is configured to transmit a data signal to the storage sub-circuit in response to a control signal;   wherein the driving sub-circuit comprises a control electrode, a first electrode and a second electrode, the control electrode of the driving sub-circuit is coupled to the storage sub-circuit, the first electrode of the driving sub-circuit is configured to receive a first power source voltage, the second electrode of the driving sub-circuit is coupled to a first electrode of the light emitting element, and the driving sub-circuit is configured to drive the light emitting element to emit light in response to a voltage of the control electrode of the driving sub-circuit;   wherein the storage sub-circuit comprises a storage capacitor, the storage capacitor comprises a first capacitor electrode and a second capacitor electrode opposite to the first capacitor electrode, the first capacitor electrode and the second capacitor electrode are respectively configured as a first terminal of the storage sub-circuit and a second terminal of the storage sub-circuit, the second capacitor electrode is located between the base substrate and the first capacitor electrode, the second capacitor electrode comprises a first region, a second region and a third region that are arranged in a short side direction of the sub-pixel in sequence, a carrier mobility in the second region is different from a carrier mobility in the first region and a carrier mobility in the third region, and an area of the second region is larger than an area of the first region and an area of the third region;   wherein the control electrode of the driving sub-circuit and the first capacitor electrode are disposed in the same layer and are a continuous integral structure; and   wherein the data writing sub-circuit, the storage sub-circuit and the driving sub-circuit are sequentially arranged along a direction parallel to the base substrate and perpendicular to the short side direction of the sub-pixel.   
     
     
         2 . The display panel according to  claim 1 , wherein the pixel circuit further comprises a resistor, the resistor is connected in series between the second electrode of the driving sub-circuit and the first electrode of the light emitting element, the resistor and the driving electrode of the driving sub-circuit are disposed in the same layer and spaced from each other, and a resistivity of the resistor is higher than a resistivity of the control electrode of the driving sub-circuit. 
     
     
         3 . The display panel according to  claim 2 , wherein the data writing sub-circuit comprises a transmission gate circuit, the transmission gate circuit comprises a first data writing transistor and a second data writing transistor, each of the first data writing transistor and the second data writing transistor comprises a gate electrode, a first electrode and a second electrode, the control signal comprises a first control signal and a second signal;
 wherein the gate electrode of the first data writing transistor is configured to receive the first control signal, the gate electrode of the second data writing transistor is configured to receive the second control signal, the first electrode of the first data writing transistor is coupled to the first electrode of the second data writing transistor, and each of the first electrode of the first data writing transistor and the first electrode of the second data writing transistor is coupled to the first terminal of the storage sub-circuit and the control electrode of the driving sub-circuit, the second electrode of the first data writing transistor is coupled to the second electrode of the second data writing transistor, and each of the second electrode of the first data writing transistor and the second electrode of the second data writing transistor is configured to receive the data signal.   
     
     
         4 . The display panel according to  claim 3 , wherein the driving sub-circuit comprises a driving transistor, a gate electrode of the driving transistor, a first electrode of the driving transistor, and a second electrode of the driving transistor are configured as the control electrode of the driving sub-circuit, the first electrode of the driving sub-circuit, and the second electrode of the driving sub-circuit, respectively. 
     
     
         5 . The display panel according to  claim 4 , wherein each of the first data writing transistor and the driving transistor is an N-type metal oxide semiconductor field effect transistor, and the second data writing transistor is a P-type metal oxide semiconductor field effect transistor. 
     
     
         6 . The display panel according to  claim 5 , wherein the transmission gate circuit and the driving transistor are respectively located on both sides of the storage capacitor in a first direction parallel to the base substrate. 
     
     
         7 . The display panel according to  claim 6 , wherein the resistor and the driving transistor are located on the same side of the storage capacitor in the first direction parallel to the base substrate. 
     
     
         8 . The display panel according to  claim 7 , wherein a minimum distance between a channel of the driving transistor and the first data writing transistor is greater than a minimum distance between the channel of the driving transistor and the second data writing transistor;
 wherein a minimum distance between the resistor and the first data writing transistor is smaller than a minimum distance between the resistor and the second data writing transistor;   wherein in a second direction parallel to the base substrate and perpendicular to the first direction, the second data writing transistor and the first data writing transistor are arranged in sequence and the driving transistor and the resistor are arranged in sequence, wherein the second direction is the short side direction of the sub-pixel.   
     
     
         9 . The display panel according to  claim 8 , wherein the resistor has an elongated shape extending in the first direction, and the resistor is located on a side of the second electrode of the driving transistor away from the driving transistor;
 wherein a width of the resistor is smaller than a width of one of the gate electrode of the first data writing transistor, the gate electrode of the second data writing transistor, and the gate electrode of the driving transistor.   
     
     
         10 . The display panel according to  claim 5 , wherein the gate electrode of the driving transistor, the gate electrode of the first data writing transistor, the gate electrode of the second data writing transistor, the first capacitor electrode, and the resistor are disposed in the same layer. 
     
     
         11 . The display panel according to  claim 5 , wherein the storage capacitor further comprises a third capacitor electrode, the third capacitor electrode is located on a side of the first capacitor electrode away from the second capacitor electrode in a direction perpendicular to the base substrate, and the third capacitor electrode is coupled to the first region of the second capacitor electrode through a first via hole;
 wherein an orthographic projection of the third capacitor electrode on the base substrate falls within an orthographic projection of the second capacitor electrode on the base substrate, and the orthographic projection of the third capacitor electrode on the base substrate partially overlaps with an orthographic projection of the first capacitor electrode on the base substrate.   
     
     
         12 . The display panel according to  claim 11 , wherein the display panel further comprises a grounding line configured to couple the first region and the third region of the second capacitor electrode, so that the first region and the third region of the second capacitor electrode input a grounding voltage, the grounding line is located on a side of the third capacitor electrode away from the second capacitor electrode in the direction perpendicular to the base substrate, and an orthographic projection of the grounding line on the base substrate partially overlaps with the orthographic projection of the third capacitor electrode on the base substrate. 
     
     
         13 . The display panel according to  claim 8 , wherein the second data writing transistor and the first data writing transistor are disposed side by side along the second direction, and are arranged symmetrically with respect to a symmetric axis in the first direction. 
     
     
         14 . The display panel according to  claim 5 , wherein the display panel comprises four said sub-pixels, and the four sub-pixels constitute a pixel unit group;
 wherein the four sub-pixels are arranged in a first direction and a second direction as an array, and the first direction is perpendicular to the second direction; and   wherein orthographic projections of second data writing transistors of the four sub-pixels on the base substrate fall within one N-type well region in the base substrate.   
     
     
         15 . The display panel according to  claim 14 , wherein resistors of the sub-pixels adjacent in the first direction are arranged symmetrically with respect to a symmetric axis in the second direction, and resistors of the sub-pixels adjacent in the second direction are arranged symmetrically with respect to a symmetric axis in the first direction;
 wherein transmission gate circuits of two sub-pixels adjacent in the first direction are arranged symmetrically with respect to a symmetric axis in the second direction, and transmission gate circuits of two sub-pixels adjacent in the second direction are arranged symmetrically with respect to a symmetric axis in the first direction;   wherein driving transistors of the two sub-pixels adjacent in the first direction are arranged symmetrically with respect to a symmetric axis in the second direction, and driving transistors of the two sub-pixels adjacent in the second direction are arranged symmetrically with respect to a symmetric axis in the first direction;   wherein first capacitor electrodes of the sub-pixels adjacent in the first direction are arranged symmetrically with respect to a symmetric axis in the second direction, and first capacitor electrodes of the sub-pixels adjacent in the second direction are arranged symmetrically with respect to a symmetric axis in the first direction.   
     
     
         16 . The display panel according to  claim 15 , wherein orthographic projections of the first capacitor electrodes of the four sub-pixels on the base substrate are located outside the N-type well region, and are disposed surrounding the N-type well region. 
     
     
         17 . The display panel according to  claim 11 , wherein a part of the third capacitor electrode close to the first region of the second capacitor electrode has a width in the first direction being greater than a width in the first direction of a part of the third capacitor electrode close to the third region of the second capacitor electrode;
 wherein the sub-pixel further comprises an anode via hole configured to connect the pixel circuit and the light emitting element, and an orthographic projection of the anode via hole on the base substrate at least partially overlaps with the orthographic projection of the first capacitor electrode on the base substrate;   wherein the sub-pixel further comprises an anode via hole configured to connect the pixel circuit and the light emitting element, and an orthographic projection of the anode via hole on the base substrate at least partially overlaps with the orthographic projection of the third capacitor electrode on the base substrate.   
     
     
         18 . The display panel according to  claim 1 , wherein the pixel circuit further comprises:
 a connecting electrode configured to couple the data writing sub-circuit and the first capacitor electrode of the storage capacitor,   wherein the connecting electrode is coupled to the first capacitor electrode through a second via hole, and a distance between the second via hole and the first region is smaller than a distance between the second via hole and the third region.   
     
     
         19 . The display panel according to  claim 11 , wherein a distance between the first via hole and the driving transistor is smaller than a distance between the first via hole and the data writing sub-circuit;
 wherein the orthographic projection of the first capacitor electrode on the base substrate and the orthographic projection of the second capacitor electrode on the base substrate have an overlapped region, and the overlapped region comprises a first protrusion protruding toward the driving transistor and a second protrusion protruding toward the first data writing transistor.   
     
     
         20 . A display device, comprising the display panel according to  claim 1 .