Clock selection method for multiplying delay locked loop

Abstract

There is provided a method for generating a select signal for a multiplexer of a Multiplying Delay Locked Loop (MDLL). The method includes determining that an output of a divider of the MDLL is a high level, determining that an output signal of a multiplexed voltage controlled oscillator (VCO) of the MDLL is a falling edge after the output of the divider is the high level and inserting a select signal as a select input to the multiplexer at the falling edge of the output signal of the multiplexed VCO in response to determining that the output of the divider has achieved the high level.

What is claimed: 
     
         1 . A method for generating a select signal for a multiplexer of a Multiplying Delay Locked Loop (MDLL), the method comprising:
 determining that an output of a divider of the MDLL is a high level;   determining that an output signal of a multiplexed voltage controlled oscillator (VCO) of the MDLL is a falling edge after the output of the divider is the high level; and   inserting a select signal with the high level as a select input to the multiplexer at the falling edge of the output signal of the multiplexed VCO based on the output of the divider having the high level.   
     
     
         2 . The method as claimed in  claim 1 , wherein the select signal is generated based on the output signal of the multiplexed VCO, a reference signal and the output of the divider. 
     
     
         3 . The method as claimed in  claim 1 , wherein the select signal is generated using a select signal generation circuit, and wherein the select signal generation circuit comprises:
 a plurality of D-flip flops, wherein the output signal of the multiplexed VCO and the output of the divider is input to the plurality of D-flip flops; and   a plurality of logic gates.   
     
     
         4 . The method as claimed in  claim 1 , wherein the select signal is the high level at a second falling edge of the output signal of the multiplexed VCO when the output of the divider has achieved a rising edge. 
     
     
         5 . The method as claimed in  claim 1 , wherein the select signal is the high level at a third falling edge of the output signal of the multiplexed VCO when the output of the divider has achieved a rising edge. 
     
     
         6 . The method as claimed in  claim 1 , wherein the select signal is a low level at a first rising edge of the output signal of the multiplexed VCO, after the select signal is made the high level, when a reference signal is the high level. 
     
     
         7 . The method as claimed in  claim 1 , wherein the select signal is a low level at a rising edge of a reference signal, when output signal of the multiplexed VCO has achieved a first rising edge after the select signal is made the high level. 
     
     
         8 . The method as claimed in  claim 1 , wherein the inserting the select signal as the select input to the multiplexer at the falling edge of the output signal of the multiplexed VCO comprises:
 determining that the falling edge of the output signal of the multiplexed VCO is a second falling edge; and   inserting the select signal at the second falling edge of the output signal of the multiplexed VCO.   
     
     
         9 . The method as claimed in  claim 1 , wherein the inserting the select signal as the select input to the multiplexer at the falling edge of the output signal of the multiplexed VCO comprises:
 determining that the falling edge of the output signal of the multiplexed VCO is a third falling edge; and   inserting the select signal at the third falling edge of the output signal of the multiplexed VCO.   
     
     
         10 . The method as claimed in  claim 9 , wherein the method further comprises:
 determining that the select signal is the high level;   determining that the output signal of the multiplexed VCO is a rising edge;   determining that a reference signal is the high level; and   de-inserting the select signal as the select input to the multiplexer at the rising edge of the output signal of the multiplexed VCO and wherein the reference signal is the high level.   
     
     
         11 . The method as claimed in  claim 10  wherein the de-inserting the select signal as the select input to the multiplexer at the rising edge of the output signal of the multiplexed VCO comprises:
 determining that the rising edge of the output signal of the multiplexed VCO is a first rising edge; and 
 de-inserting the select signal at the first rising edge of the output signal of the multiplexed VCO and the reference signal is the high level. 
 
     
     
         12 . The method as claimed in  claim 11 , wherein the de-inserting the select signal as the select input to the multiplexer at the rising edge of the output signal of the multiplexed VCO comprises:
 determining that the rising edge of the output signal of the multiplexed VCO is a first rising edge after the select signal is the high level;   determining that the reference signal is a low level at the first rising edge of the output signal of the multiplexed VCO and the reference signal has a rising edge after the first rising edge of the output signal of the multiplexed VCO; and   de-inserting the select signal at the rising edge of the reference signal.   
     
     
         13 . The method as claimed in  claim 1 , wherein the select signal is selected as the select input to the multiplexer based on the output of the divider and output signal of the multiplexed VCO for insertion. 
     
     
         14 . The method as claimed in  claim 1 , wherein the select signal is selected as in as the select input to the multiplexer based on a reference signal and output signal of the multiplexed VCO for de-insertion. 
     
     
         15 . An apparatus comprising:
 a first circuit configured to determine that an output of a divider of a Multiplying Delay Locked Loop (MDLL) is a high level;   a second circuit configured to determine that an output signal of a multiplexed voltage controlled oscillator (VCO) of the MDLL is a falling edge after the output of the divider is the high level; and   a third circuit configured to generate a select signal with the high level to be inserted as a select input to a multiplexer of the MDLL at the falling edge of the output signal of the multiplexed VCO based on a determination that the output of the divider has the high level.   
     
     
         16 . The apparatus of  claim 15 , wherein the select signal is generated based on the output signal of the multiplexed VCO, a reference signal and the output of the divider. 
     
     
         17 . The apparatus of  claim 15 , wherein the third circuit is signal generation circuit comprising:
 a plurality of D-flip flops, wherein the input to the plurality of D-flip flops is the output signal of the multiplexed VCO and the output of the divider; and   a plurality of logic gates.   
     
     
         18 . The apparatus of  claim 15 , wherein the third circuit is further configured to:
 determine that the falling edge of the output signal of the multiplexed VCO is a third falling edge; and   generate the select signal at the third falling edge of the output signal of the multiplexed VCO.