Semiconductor integrated circuit device

Abstract

In an IO region of a semiconductor integrated circuit device, placed is an IO cell row including a signal IO cell and a power IO cell supplying a first power supply. The power IO cell includes first and second external terminals connected to an external connection pad and an electrostatic discharge (ESD) protection device formed at least in a region between the first and second external terminals. The first external terminal is placed at a position having an overlap in the Y direction with a power supply line for a second power supply.

What is claimed is: 
     
         1 . A semiconductor integrated circuit device, comprising:
 a chip;   a core region provided on the chip;   an IO region provided on the chip; and   an IO cell row placed in the IO region, including a plurality of IO cells arranged in a first direction that is a direction along an outer edge of the chip,   
       wherein
 the plurality of IO cells include
 a signal IO cell performing input, output, or input/output of a signal, and 
 a power IO cell supplying a first power supply to at least either the core region or the IO region, 
 
 the power IO cell includes
 an external connection pad for the first power supply, 
 first and second external terminals arranged along a second direction perpendicular to the first direction and connected to the external connection pad, and 
 an electrostatic discharge (ESD) protection device electrically connected between the first power supply and a second power supply, formed at least in a region between the first external terminal and the second external terminal along the second direction, and connected to the first and second external terminals, 
 
 each of the first and second external terminals connects the first power supply and the ESD protection device, 
 in the signal IO cell, a plurality of power supply lines for the second power supply extending in the first direction are placed, and 
 the second external terminal is placed at a position having an overlap in the second direction, with one of the plurality of power supply lines. 
 
     
     
         2 . The semiconductor integrated circuit device of  claim 1 , wherein
 the power IO cell includes
 a third external terminal connected to the external connection pad for the first power supply and also connected to the ESD protection device, and 
   the third external terminal is placed at a position having an overlap in the second direction with one of the plurality of power supply lines.   
     
     
         3 . The semiconductor integrated circuit device of  claim 1 , wherein
 at least one of the plurality of power supply lines passes through the power IO cell.   
     
     
         4 . The semiconductor integrated circuit device of  claim 1 , wherein
 in the power IO cell, a power supply line for the first power supply extending in the first direction is placed between the first external terminal and the second external terminal.   
     
     
         5 . The semiconductor integrated circuit device of  claim 1 , wherein
 the ESD protection device is disposed closer to the core region than the external connection pad.   
     
     
         6 . The semiconductor integrated circuit device of  claim 2 , wherein:
 the ESD protection device includes a transistor having a source, a gate and a drain, and   the first external terminal and the second external terminals are connected one of the source or the drain, and the third external terminal is connected to another of the source or the drain.