Voltage regulator and signal amplifying circuit

Abstract

A voltage regulator includes an error amplifier circuit, an output stage circuit and an output feedback path. The error amplifier circuit includes a first-stage amplifier and a second-stage amplifier. The first-stage amplifier is configured to amplify a difference between an output feedback signal and a reference signal to generate a first differential signal and a second differential signal. The second-stage amplifier is configured to amplify a difference between the first differential signal and the second differential signal to generate an output control signal. The output stage circuit is coupled with a first power terminal, and includes a switch. The switch is configured to generate an output signal at an output node according to the output control signal. The output feedback path is coupled with the output node and the error amplifier circuit, and is configured to generate the output feedback signal according to the output signal.

What is claimed is: 
     
         1 . A voltage regulator, comprising:
 an error amplifier circuit, comprising:   a first-stage amplifier, comprising:
 a first current source, coupled with a first power terminal; 
 a fully differential amplifier circuit, coupled between the first current source and a second power terminal, and configured to amplify a difference between an output feedback signal and a reference signal to generate a first differential signal and a second differential signal; and 
 a common mode feedback circuit, configured to provide a common mode feedback signal to the fully differential amplifier circuit so as to stabilize a direct-current common mode voltage of the first differential signal and the second differential signal, wherein the common mode feedback circuit comprises:
 a first amplifier circuit, configured to amplify a difference between the first differential signal and a common mode control signal to generate a first output current; and 
 a second amplifier circuit, configured to amplify a difference between the second differential signal and the common mode control signal to generate a second output current, 
 wherein the common mode feedback circuit is configured to generate the common mode feedback signal according to the first output current and the second output current; 
 
   a second-stage amplifier, configured to amplify a difference between the first differential signal and the second differential signal to generate an output control signal;   an output stage circuit, coupled with the first power terminal and comprising a switch, wherein the switch is configured to generate an output signal at an output node according to the output control signal; and   an output feedback path, coupled with the output node and the error amplifier circuit, and configured to generate the output feedback signal according to the output signal.   
     
     
         2 . The voltage regulator of  claim 1 , wherein the fully differential amplifier circuit comprises:
 a first transistor, coupled between the first current source and a first differential node, and controlled by the output feedback signal to generate the first differential signal at the first differential node;   a second transistor, coupled between the first current source and a second differential node, and controlled by the reference signal to generate the second differential signal at the second differential node;   a third transistor, coupled between the first differential node and the second power terminal, and controlled by the common mode feedback signal; and   a fourth transistor, coupled between the second differential node and the second power terminal, and controlled by the common mode feedback signal.   
     
     
         3 . The voltage regulator of  claim 1 , wherein the first amplifier circuit comprises:
 a second current source, coupled with the first power terminal;   a fifth transistor, coupled between the second current source and a first node, and controlled by the first differential signal;   a sixth transistor, coupled between the second current source and a second node, and controlled by the common mode control signal to provide the first output current to the second node;   a seventh transistor, wherein a first terminal and a control terminal of the seventh transistor are coupled with the first node and a third node, and a second terminal of the seventh transistor is coupled with the second power terminal; and   an eighth transistor, wherein a first terminal and a control terminal of the eighth transistor are coupled with the second node and a fourth node, and a second terminal of the eighth transistor is coupled with the second power terminal,   wherein the second amplifier circuit comprises:   a third current source, coupled with the first power terminal;   the seventh transistor;   the eighth transistor;   a ninth transistor, coupled between the third current source and the fourth node, and controlled by the common mode control signal to provide the second output current to the fourth node; and   a tenth transistor, coupled between the third current source and the third node, and controlled by the second differential signal.   
     
     
         4 . The voltage regulator of  claim 1 , wherein the second-stage amplifier comprises:
 a differential to single-ended amplifier, coupled with the first power terminal, and configured to amplify the difference between the first differential signal and the second differential signal to output an error amplifying signal, wherein the voltage regulator generates the output control signal according to the error amplifying signal; and   a fourth current source, coupled between the differential to single-ended amplifier and the second power terminal.   
     
     
         5 . The voltage regulator of  claim 4 , wherein the differential to single-ended amplifier comprises:
 an eleventh transistor, coupled between the first power terminal and an inverting node;   a twelfth transistor, coupled between the first power terminal and a gain node, wherein the gain node is configured to provide the error amplifying signal, and a control terminal of the eleventh transistor and a control terminal of the twelfth transistor are coupled with the inverting node;   a thirteenth transistor, coupled between the inverting node and the fourth current source, and controlled by the second differential signal; and   a fourteenth transistor, coupled between the gain node and the fourth current source, and controlled by the first differential signal.   
     
     
         6 . The voltage regulator of  claim 4 , wherein the error amplifier circuit further comprises a buffer circuit, and the buffer circuit comprises:
 a fifth current source, coupled between the first power terminal and a driving node;   a sixth current source, coupled with the second power terminal; and   a fifteenth transistor, coupled between the driving node and the sixth current source, and controlled by the error amplifying signal to provide an adjusted error amplifying signal at the driving node as the output control signal.   
     
     
         7 . The voltage regulator of  claim 6 , wherein the first current source comprises a sixteenth transistor coupled between the first power terminal and the fully differential amplifier circuit,
 the fourth current source comprises a seventeenth transistor coupled between the differential to single-ended amplifier and the second power terminal,   the fifth current source comprises an eighteenth transistor coupled between the first power terminal and the driving node,   the sixth current source comprises a nineteenth transistor coupled between the fifteenth transistor and the second power terminal,   wherein a control terminal of the sixteenth transistor and a control terminal of the eighteenth transistor are configured to receive a first bias signal, and a control terminal of the seventeenth transistor and a control terminal of the nineteenth transistor are configured to receive a second bias signal.   
     
     
         8 . The voltage regulator of  claim 1 , wherein the output feedback path comprises:
 a first voltage dividing resistor, configured to receive the output signal; and   a second voltage dividing resistor, coupled with the first voltage dividing resistor in series, wherein the first voltage dividing resistor and the second voltage dividing resistor are configured to perform voltage division to the output signal to generate the output feedback signal.   
     
     
         9 . The voltage regulator of  claim 1 , wherein the output feedback path is configured to transmit the output signal to the error amplifier circuit as the output feedback signal. 
     
     
         10 . A signal amplifying circuit, comprising:
 an error amplifier circuit, comprising:   a first-stage amplifier, comprising:
 a first current source, coupled with a first power terminal; 
 a fully differential amplifier circuit, coupled between the first current source and a second power terminal, and configured to amplify a difference between a first input signal and a second input signal to generate a first differential signal and a second differential signal; and 
 a common mode feedback circuit, configured to provide a common mode feedback signal to the fully differential amplifier circuit so as to stabilize a direct-current common mode voltage of the first differential signal and the second differential signal, wherein the common mode feedback circuit comprises:
 a first amplifier circuit, configured to amplify a difference between the first differential signal and a common mode control signal to generate a first output current; and 
 a second amplifier circuit, configured to amplify a difference between the second differential signal and the common mode control signal to generate a second output current; 
 wherein the common mode feedback circuit is configured to generate the common mode feedback signal according to the first output current and the second output current; 
 
   a second-stage amplifier, configured to amplify a difference between the first differential signal and the second differential signal to generate an output control signal; and   an output stage circuit, coupled with the first power terminal and comprising a switch, wherein the switch is configured to generate an output signal at an output node according to the output control signal.   
     
     
         11 . The signal amplifying circuit of  claim 10 , wherein the fully differential amplifier circuit comprises:
 a first transistor, coupled between the first current source and a first differential node, and controlled by the first input signal to generate the first differential signal at the first differential node;   a second transistor, coupled between the first current source and a second differential node, and controlled by the second input signal to generate the second differential signal at the second differential node;   a third transistor, coupled between the first differential node and the second power terminal, and controlled by the common mode feedback signal; and   a fourth transistor, coupled between the second differential node and the second power terminal, and controlled by the common mode feedback signal.   
     
     
         12 . The signal amplifying circuit of  claim 10 , wherein the first amplifier circuit comprises:
 a second current source, coupled with the first power terminal;   a fifth transistor, coupled between the second current source and a first node, and controlled by the first differential signal;   a sixth transistor, coupled between the second current source and a second node, and controlled by the common mode control signal to provide the first output current to the second node;   a seventh transistor, wherein a first terminal and a control terminal of the seventh transistor are coupled with the first node and a third node, and a second terminal of the seventh transistor is coupled with the second power terminal; and   an eighth transistor, wherein a first terminal and a control terminal of the eighth transistor are coupled with the second node and a fourth node, and a second terminal of the eighth transistor is coupled with the second power terminal,   wherein the second amplifier circuit comprises:   a third current source, coupled with the first power terminal;   the seventh transistor;   the eighth transistor;   a ninth transistor, coupled between the third current source and the fourth node, and controlled by the common mode control signal to provide the second output current to the fourth node; and   a tenth transistor, coupled between the third current source and the third node, and controlled by the second differential signal.   
     
     
         13 . The signal amplifying circuit of  claim 10 , wherein the second-stage amplifier comprises:
 a differential to single-ended amplifier, coupled with the first power terminal, and configured to amplify the difference between the first differential signal and the second differential signal to output an error amplifying signal, wherein the signal amplifying circuit generates the output control signal according to the error amplifying signal; and   a fourth current source, coupled between the differential to single-ended amplifier and the second power terminal.   
     
     
         14 . The signal amplifying circuit of  claim 13 , wherein the differential to single-ended amplifier comprises:
 an eleventh transistor, coupled between the first power terminal and an inverting node;   a twelfth transistor, coupled between the first power terminal and a gain node, wherein the gain node is configured to provide the error amplifying signal, and a control terminal of the eleventh transistor and a control terminal of the twelfth transistor are coupled with the inverting node;   a thirteenth transistor, coupled between the inverting node and the fourth current source, and controlled by the second differential signal; and   a fourteenth transistor, coupled between the gain node and the fourth current source, and controlled by the first differential signal.   
     
     
         15 . The signal amplifying circuit of  claim 13 , wherein the error amplifier circuit further comprises a buffer circuit, and the buffer circuit comprises:
 a fifth current source, coupled between the first power terminal and a driving node;   a sixth current source, coupled with the second power terminal; and   a fifteenth transistor, coupled between the driving node and the sixth current source, and controlled by the error amplifying signal to provide an adjusted error amplifying signal at the driving node as the output control signal.   
     
     
         16 . The signal amplifying circuit of  claim 15 , wherein the first current source comprises a sixteenth transistor coupled between the first power terminal and the fully differential amplifier circuit,
 the fourth current source comprises a seventeenth transistor coupled between the differential to single-ended amplifier and the second power terminal,   the fifth current source comprises an eighteenth transistor coupled between the first power terminal and the driving node,   the sixth current source comprises a nineteenth transistor coupled between the fifteenth transistor and the second power terminal,   wherein a control terminal of the sixteenth transistor and a control terminal of the eighteenth transistor are configured to receive a first bias signal, and a control terminal of the seventeenth transistor and a control terminal of the nineteenth transistor are configured to receive a second bias signal.