Apparatus operating in geardown mode

Abstract

Methods, apparatuses, and systems related to an apparatus implementing a geardown mode in a parallel pipeline configuration. The apparatus can include mechanisms to manage signal timing across multiple data processing pipelines for different communication speeds. While operating in a geardown mode, the apparatus can capture a sync pulse in two or more data pipelines. The apparatus can identify the pipeline that first captured the sync pulse and suppress the operation of the other pipelines.

We claim: 
     
         1 . An apparatus, comprising:
 an even pipeline configured to process a portion of data according to an even internal clock produced by dividing an external clock;   an odd pipeline configured to process another portion of data according to an odd internal clock produced by dividing the external clock, the odd internal clock being complementary to the even internal clock;   a command circuit, in a geardown mode, configured to:
 identify that a memory operation command was received on one of the even and odd pipelines prior to the other of the even and odd pipelines; 
 block the other of the even and odd pipelines to prevent the memory operation command from being decoded in and propagating through the other of the even and odd pipelines; and 
 perform the memory operation command through the one of the even and odd pipelines according to the even internal clock or the odd internal clock. 
   
     
     
         2 . The apparatus of  claim 1 , wherein the command circuit is configured to:
 in response to receiving a model predictive control command and the memory operation command,
 enter the geardown mode, and 
 utilize one of the even and odd pipelines that first received the memory operation command instead of utilizing both the even and odd pipelines to perform the memory operation. 
   
     
     
         3 . The apparatus of  claim 1 , wherein the command circuit is configured to:
 in response to performing a self-refresh entry or exit sequence,
 enter the geardown mode, and 
 utilize one of the even and odd pipelines that first received the memory operation command instead of utilizing both the even and odd pipelines to perform the memory operation. 
   
     
     
         4 . The apparatus of  claim 1 , wherein blocking the other of the even and odd pipelines includes:
 generating a mask command for the other of the even and odd pipelines;   resetting a first clock used to capture command address bits in the other of the even and odd pipelines; and   resetting a second clock used to capture a decoded command in the other of the even and odd pipelines.   
     
     
         5 . The apparatus of  claim 1 , wherein:
 the memory operation command is a first no-operation (NOP) command of a self-refresh exit sequence.   
     
     
         6 . The apparatus of  claim 1 , wherein:
 the apparatus comprises a Double Data Rate (DDR) Dynamic Random-Access Memory (DRAM) device.   
     
     
         7 . The apparatus of  claim 1 , wherein the apparatus comprises:
 a storage array configured to store data;   an external clock circuit configured to receive an external clock having an external frequency, wherein the external clock is shared with an external device; and   a command circuit coupled to the external clock circuit and configured to receive commands from the external device for performing memory operations.   
     
     
         8 . The apparatus of  claim 1 , wherein the command circuit is configured to:
 identify that the apparatus is operating in the geardown mode, wherein the geardown mode configures the apparatus to perform memory operations at a reduced frequency that is less than an external frequency; and   receive the memory operation command on the even pipeline and the odd pipeline while operating in the geardown mode.   
     
     
         9 . The apparatus of  claim 8 , wherein:
 the even internal clock and the odd internal clock have an internal frequency that is half of an external frequency of the external clock; and   the reduced frequency is half of the external frequency.   
     
     
         10 . A memory system comprising:
 a memory controller;   a memory array operably coupled to the memory controller;
 wherein the memory array comprises: 
 an even pipeline configured to process a portion of data according to an even internal clock produced by dividing an external clock; and 
 an odd pipeline configured to process another portion of data according to an odd internal clock produced by dividing the external clock, the odd internal clock being complementary to the even internal clock; 
 the memory array, in a geardown mode, configured to:
 identify that a memory operation command was received on one of the even and odd pipelines prior to the other of the even and odd pipelines; 
 block the other of the even and odd pipelines to prevent the memory operation command from being decoded in and propagating through the other of the even and odd pipelines; and 
 perform the memory operation command through the one of the even and odd pipelines according to the even internal clock or the odd internal clock. 
 
   
     
     
         11 . The memory system of  claim 10 , wherein the memory array is further configured to:
 in response to receiving a model predictive control command and the memory operation command,
 enter the geardown mode, and 
 utilize one of the even and odd pipelines that first received the memory operation command instead of utilizing both the even and odd pipelines to perform the memory operation. 
   
     
     
         12 . The memory system of  claim 10 , wherein the memory array is further configured to:
 in response to performing a self-refresh entry or exit sequence,
 enter the geardown mode, and 
 utilize one of the even and odd pipelines that first received the memory operation command instead of utilizing both the even and odd pipelines to perform the memory operation. 
   
     
     
         13 . The memory system of  claim 10 , wherein blocking the odd pipeline includes:
 generating a mask command for the other of the even and odd pipelines;   resetting a first clock used to capture command address bits in the other of the even and odd pipelines; and   resetting a second clock used to capture a decoded command in the other of the even and odd pipelines.   
     
     
         14 . The memory system of  claim 10 , wherein:
 the even internal clock and the odd internal clock have an internal frequency that is half of an external frequency of an external clock.   
     
     
         15 . The memory system of  claim 10 , wherein the memory operation command is a first no-operation (NOP) command of a self-refresh exit sequence. 
     
     
         16 . A method comprising:
 identifying that an apparatus is operating in a geardown mode, wherein the geardown mode configures the apparatus to perform memory operations at a reduced frequency that is less than an external frequency,
 wherein the apparatus comprises an even pipeline and an odd pipeline configured to process data according to received commands, wherein the even pipeline and the odd pipeline are each configured to process a portion of the data according to an even internal clock and an odd internal clock that respectively correspond to alternating portions or periods of an external clock; 
   receiving a memory operation command on the even pipeline and the odd pipeline while operating in the geardown mode;   identifying that the memory operation command was received on the even pipeline prior to the odd pipeline;   blocking the odd pipeline to prevent the memory operation command from being decoded in and propagating through the odd pipeline; and   performing a memory operation that corresponds to the memory operation through the even pipeline according to the even internal clock and without using the odd pipeline in the geardown mode.   
     
     
         17 . The method of  claim 16 , further comprising:
 in response to receiving a model predictive control command and the memory operation command,
 entering the geardown mode, and 
 utilizing one of the even and odd pipelines that first received the memory operation command instead of utilizing both the even and odd pipelines to perform the memory operation. 
   
     
     
         18 . The method of  claim 16 , further comprising:
 in response to performing a self-refresh entry or exit sequence,
 enter the geardown mode, and 
 utilize one of the even and odd pipelines that first received the memory operation command instead of utilizing both the even and odd pipelines to perform the memory operation. 
   
     
     
         19 . The method of  claim 16 , wherein blocking the odd pipeline includes:
 generating a mask command for the odd pipeline;   resetting a first clock used to capture command address bits in the odd pipeline; and   resetting a second clock used to capture a decoded command in the odd pipeline.   
     
     
         20 . The method of  claim 16 , the even internal clock and the odd internal clock have an internal frequency that is half of the external frequency of the external clock, and wherein the reduced frequency is half of the external frequency.