US12495570B2ActiveUtilityA1

Vertical field-effect transistor, method for producing a vertical field-effect transistor and component having vertical field-effect transistors

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Assignee: BOSCH GMBH ROBERTPriority: Feb 18, 2020Filed: Feb 15, 2021Granted: Dec 9, 2025
Est. expiryFeb 18, 2040(~13.6 yrs left)· nominal 20-yr term from priority
H10D 64/251H10D 62/8503H10D 30/015H10D 8/60H10D 64/411H10D 62/343H10D 62/106H10D 62/114H10D 30/477H10D 30/478H10D 64/256
49
PatentIndex Score
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Cited by
23
References
13
Claims

Abstract

A vertical field-effect transistor. The vertical field-effect transistor has: A first semiconductor layer, which has a p-type conductivity, on or over a drift region; a groove structure which penetrates the first semiconductor layer vertically, the groove structure having at least one side wall on which a field-effect transistor (FET)-channel region is formed, the FET-channel region having a III-V-heterostructure for forming a two-dimensional electron gas at an interface of the III-V-heterostructure; a source-drain electrode which is electroconductively connected to the III-V-heterostructure; and a contact structure at least partially on or over the drift region, which forms a Schottky- or hetero-contact at least with the drift region, the contact structure being electroconductively connected to the source-drain electrode, and at least the region lying vertically between the contact structure and the drift region being free of the first semiconductor layer.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
         1 . A vertical field-effect transistor, comprising:
 a first semiconductor layer, which has a p-type conductivity, situated on or over a drift region;   a groove structure which penetrates the first semiconductor layer vertically, the groove structure having at least one side wall on which a field-effect transistor (FET)-channel region is formed, the FET-channel region having a III-V-heterostructure for forming a two-dimensional electron gas at an interface of the III-V-heterostructure;   a source-drain electrode, which is electroconductively connected to the III-V-heterostructure; and   a contact structure at least partially on or over the drift region, which forms a Schottky- or hetero-contact at least with the drift region, the contact structure being electroconductively connected to the source-drain electrode   wherein at least a region lying vertically between the contact structure and the drift region is free of the first semiconductor layer.   
     
     
         2 . The vertical field-effect transistor as recited in  claim 1 , wherein the contact structure is formed on the III-V-heterostructure. 
     
     
         3 . The vertical field-effect transistor as recited in  claim 1 , wherein the contact structure is formed directly on the drift region. 
     
     
         4 . The vertical field-effect transistor as recited in  claim 1 , wherein the contact structure is formed laterally next to the groove structure. 
     
     
         5 . The vertical field-effect transistor as recited in  claim 1 , further comprising:
 a shielding structure which has a p-type conductivity, the shielding structure being electroconductively connected to the source-drain electrode, and the shielding structure extending further in a direction of the drift region or into the drift region than the III-V-heterostructure; and   wherein the contact structure is formed laterally between the groove structure and the shielding structure.   
     
     
         6 . The vertical field-effect transistor as recited in  claim 1 , wherein the groove structure has a first side wall and a second side wall which encompass a bottom, the contact structure being formed over the bottom and/or one of the first and second side walls on the III-V-heterostructure. 
     
     
         7 . The vertical field-effect transistor as recited in  claim 6 , further comprising an insulating layer and a gate electrode on or over the III-V-heterostructure, the insulating layer being formed between the contact structure and the gate electrode. 
     
     
         8 . The vertical field-effect transistor as recited in  claim 1 , wherein:
 the groove structure has a strip form or hexagonal form in a longitudinal direction, perpendicular to a vertical direction, and the contact structure has a pillar-type cross-sectional form in a longitudinal direction; or   the contact structure has a strip form that extends laterally over a width of the vertical field-effect transistor.   
     
     
         9 . The vertical field-effect transistor as recited in  claim 1 , wherein: (i) the contact structure is part of a Schottky diode, or (ii) the contact structure is part of a hetero diode and includes polysilicon. 
     
     
         10 . The vertical field-effect transistor as recited in  claim 1 , further comprising:
 a second semiconductor layer, which is electrically insulating, on the first semiconductor layer, the groove structure penetrating the first semiconductor layer and the second semiconductor layer vertically, and at least the region lying vertically between the contact structure and the drift region being free of the first semiconductor layer and the second semiconductor layer.   
     
     
         11 . A component, comprising:
 a first vertical field-effect transistor and a second vertical field-effect transistor, each of which including:
 a first semiconductor layer, which has a p-type conductivity, on or over a drift region, 
 a groove structure which penetrates the first semiconductor layer vertically, the groove structure having at least one side wall on which a field-effect transistor (FET)-channel region is formed, the FET-channel region having a III-V-heterostructure for forming a two-dimensional electron gas at an interface of the III-V-heterostructure, and 
 a source-drain electrode, which is electroconductively connected to the III-V-heterostructure; 
   a contact structure at least partially on or over the drift region, the contact structure being formed laterally between the groove structure of the first vertical field-effect transistor and the groove structure of the second vertical field-effect transistor and being electroconductively connected to the source-drain electrode of at least one of the first and second vertical field-effect transistors, at least a region lying vertically between the contact structure and the drift region being free of the first semiconductor layer.   
     
     
         12 . The component as recited in  claim 11 , wherein each vertical field-effect transistor of the first and second vertical field-effect transistors has a shielding structure which has a p-type conductivity and is electroconductively connected to the source-drain electrode of the vertical field-effect transistor, the shielding structure extending further in the direction of the drift region or into the drift region than the III-V-heterostructure of the vertical field-effect transistor, and wherein the contact structure is formed laterally between the shielding structure of the first vertical field-effect transistor and the shielding structure of the second vertical field-effect transistor. 
     
     
         13 . A method for producing a vertical field-effect transistor, the method comprising:
 forming a first semiconductor layer, which has a p-type conductivity, on or over a drift region;   forming a groove structure which penetrates the first semiconductor layer vertically, the groove structure being formed with at least one side wall on which a field-effect transistor (FET)-channel region is formed, the FET-channel region having a III-V-heterostructure for forming a two-dimensional electron gas at an interface of the III-V-heterostructure;   forming a source-drain electrode, which is electroconductively connected to the III-V-heterostructure; and   forming a contact structure at least partially on or over the drift region, which forms a Schottky- or hetero-contact at least with the drift region, the contact structure being electroconductively connected to the source-drain electrode;   wherein at least a region lying vertically between the contact structure and the drift region remaining free of the first semiconductor layer.

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