Spacer structures for semiconductor devices

Abstract

The present disclosure describes a semiconductor device having a protection layer on inner spacer structures. The semiconductor device includes a nanostructure on a substrate. The nanostructure includes multiple semiconductor layers. The semiconductor device further includes a gate structure wrapped around a middle portion of the multiple semiconductor layers and a spacer structure adjacent to an end portion of the multiple semiconductor layers. The gate structure includes a high-k dielectric layer. The semiconductor device further includes a protection layer between the high-k dielectric layer and the spacer structure.

What is claimed is: 
     
         1 . A method, comprising:
 forming a nanostructure on a substrate, wherein the nanostructure comprises first and second sets of semiconductor layers stacked in an alternating configuration;   forming a protection layer on an end portion of the first set of semiconductor layers;   forming a spacer structure on the protection layer, wherein the spacer structure is in contact with the second set of semiconductor layers, and wherein the protection layer is in contact with the spacer structure and the first and second sets of semiconductor layers;   forming a source/drain structure in contact with the spacer structure and the second set of semiconductor layers; and   forming a gate structure to replace the first set of semiconductor layers, wherein the gate structure comprises a high-k dielectric layer in contact with the protection layer.   
     
     
         2 . The method of  claim 1 , wherein the forming the protection layer comprises:
 etching the end portion of the first set of semiconductor layers;   depositing a dielectric material on end portions of the first and second sets of semiconductor layers; and   removing the dielectric material from the end portion of the second set of semiconductor layers.   
     
     
         3 . The method of  claim 1 , further comprising etching an interfacial layer adjacent to the end portion of the first set of semiconductor layers prior to forming the protection layer. 
     
     
         4 . The method of  claim 1 , wherein forming the gate structure comprises:
 removing the first set of semiconductor layers to expose the protection layer;   depositing the high-k dielectric layer on the protection layer; and   depositing a metal gate structure on the high-k dielectric layer.   
     
     
         5 . The method of  claim 1 , wherein forming the gate structure comprises depositing the high-k dielectric layer on the protection layer. 
     
     
         6 . The method of  claim 1 , further comprising etching the first and second sets of semiconductor layers to expose end portions of the first and second sets of semiconductor layers. 
     
     
         7 . A method, comprising:
 forming a nanostructure on a substrate, wherein the nanostructure comprises first and second sets of semiconductor layers stacked in an alternating configuration;   forming a first dielectric layer on end portions of the first set of semiconductor layers;   forming a spacer structure on the first dielectric layer and in contact with the second set of semiconductor layers, wherein the first dielectric layer is in contact with the spacer structure and the first and second sets of semiconductor layers;   forming a source/drain structure in contact with the spacer structure and the second set of semiconductor layers;   forming a second dielectric layer on the first dielectric layer and the second set of semiconductor layers, wherein the second dielectric layer is thicker than the first dielectric layer; and   forming a metal gate structure on the second dielectric layer.   
     
     
         8 . The method of  claim 7 , wherein forming the first dielectric layer comprises:
 etching the end portions of the first set of semiconductor layers;   depositing a dielectric material on end portions of the first and second sets of semiconductor layers; and   removing the dielectric material from the end portions of the second set of semiconductor layers.   
     
     
         9 . The method of  claim 7 , further comprising etching an interfacial layer adjacent to the end portion of the first set of semiconductor layers prior to forming the first dielectric layer. 
     
     
         10 . The method of  claim 7 , wherein forming the second dielectric layer comprises:
 removing the first set of semiconductor layers; and   depositing a high-k dielectric material on the first dielectric layer and the second set of semiconductor layers.   
     
     
         11 . The method of  claim 7 , wherein forming the metal gate structure comprises depositing a metal on the second dielectric layer. 
     
     
         12 . The method of  claim 7 , further comprising etching the first and second sets of semiconductor layers to expose end portions of the first and second sets of semiconductor layers. 
     
     
         13 . A method, comprising:
 forming first and second sets of semiconductor layers stacked in an alternating configuration;   forming a recess at end portions of the first set of semiconductor layers;   forming a protection layer in the recess;   removing a portion of the protection layer between end portions of the second set of semiconductor layers;   forming a spacer structure on a remaining portion of the protection layer in the recess, wherein the protection layer is in contact with the spacer structure and the first and second sets of semiconductor layers;   growing a source/drain structure in contact with the end portions of the second set of semiconductor layers; and   forming a gate structure to wrap around the second set of semiconductor layers, wherein:   the gate structure comprises a high-k dielectric layer in contact with the protection layer; and   the protection layer is between the high-k dielectric layer and the source/drain structure.   
     
     
         14 . The method of  claim 13 , wherein the forming the protection layer comprises:
 depositing a high-k dielectric material in the recess and on the end portions of the second set of semiconductor layers; and   removing the high-k dielectric material from the end portions of the second set of semiconductor layers.   
     
     
         15 . The method of  claim 13 , wherein the forming the protection layer comprises depositing hafnium oxide in the recess. 
     
     
         16 . The method of  claim 13 , wherein the forming the recess at the end portions of the first set of semiconductor layers comprises:
 removing the end portions of the first set of semiconductor layers; and   removing an interfacial layer adjacent to the end portions of the first set of semiconductor layers.   
     
     
         17 . The method of  claim 13 , wherein the forming the gate structure comprises:
 removing the first set of semiconductor layers to expose the protection layer;   depositing the high-k dielectric layer on the protection layer and the second set of semiconductor layers; and   depositing a metal gate structure on the high-k dielectric layer.   
     
     
         18 . The method of  claim 17 , wherein the removing the first set of semiconductor layers comprises selectively etching the first set of semiconductor layers with fluorine-contained etchants. 
     
     
         19 . The method of  claim 13 , wherein the protection layer and the high-k dielectric layer comprise a same high-k dielectric material. 
     
     
         20 . The method of  claim 13 , wherein the forming the first and second sets of semiconductor layers comprises etching the first and second sets of semiconductor layers to expose the end portions of the first and second sets of semiconductor layers.