Scan driver and display device including the same

Abstract

Each stage of a scan driver includes a first control transistor connected between a first input terminal and a first node to operate in response to a clock signal, a second control transistor connected between a second input terminal and a second node to operate in response to the clock signal, a third control transistor connected between the first node and a first control node to operate in response to a first voltage provided through a first voltage terminal, a fourth control transistor connected between a second voltage terminal and a second control node to operate in response to potential at the first node, a fifth control transistor connected between the second control node and the first voltage terminal to operate in response to a potential at the second node, and a first capacitor connected between the second node and the second control node.

What is claimed is: 
     
         1 . A scan driver comprising:
 a plurality of stages sequentially connected to each other,   wherein each stage includes:   a first control transistor connected between a first input terminal and a first node, the first control transistor operating in response to a clock signal provided through a clock terminal;   a second control transistor connected between a second input terminal and a second node the second control transistor operating in response to the clock signal;   a third control transistor connected between the first node and a first control node, the third control transistor operating in response to a first voltage provided through a first voltage terminal;   a fourth control transistor connected between a second voltage terminal and a second control node, the fourth control transistor operating in response to a potential at the first node;   a fifth control transistor electrically connected between the second control node and the first voltage terminal, the fifth control transistor operating in response to a potential at the second node;   a first capacitor connected between the second node and the second control node; and   an output circuit configured to output a scan signal in response to a potential at the first control node and a potential at the second control node.   
     
     
         2 . The scan driver of  claim 1 , wherein the second control node of each of the stages is connected to a carry terminal, and
 wherein the carry terminal outputs the potential at the second control node as a carry signal.   
     
     
         3 . The scan driver of  claim 2 , wherein the carry terminal is connected to the second input terminal of a next stage. 
     
     
         4 . The scan driver of  claim 2 , wherein a potential difference between the second node and the second control node is substantially maintained at zero during a deactivation period of the second node. 
     
     
         5 . The scan driver of  claim 2 , wherein the output circuit includes:
 a first output transistor connected between an output terminal and the first voltage terminal, the first output transistor operating in response to the potential at the first control node; and   a second output transistor connected between the output terminal and the second voltage terminal, the second output transistor operating in response to the potential at the second control node.   
     
     
         6 . The scan driver of  claim 5 , wherein the output terminal is connected to the first input terminal of a next stage. 
     
     
         7 . The scan driver of  claim 6 , wherein the first input terminal of a first stage among the plurality of stages receives a first start signal as a previous scan signal, and
 wherein the second input terminal of the first stage receives a second start signal as a previous carry signal.   
     
     
         8 . The scan driver of  claim 6 , wherein each of the stages further includes:
 a second capacitor connected between the fifth control transistor and the second voltage terminal; and   a third capacitor connected between the first control node and the output terminal.   
     
     
         9 . The scan driver of  claim 1 , wherein the first voltage applied to the first voltage terminal has a voltage level lower than a voltage level of a second voltage applied to the second voltage terminal. 
     
     
         10 . The scan driver of  claim 1 , wherein the first control transistor includes:
 a first electrode connected to the first input terminal;   a second electrode connected to the first node; and   a third electrode to receive the clock signal, and   wherein the second control transistor includes:   a first electrode connected to the second input terminal;   a second electrode connected to the second node; and   a third electrode to receive the clock signal.   
     
     
         11 . The scan driver of  claim 10 , wherein the third control transistor includes:
 a first electrode connected to the first node;   a second electrode connected to the first control node; and   a third electrode connected to the first voltage terminal, and   wherein the fourth control transistor includes:   a first electrode connected to the second voltage terminal;   a second electrode connected to the second control node; and   a third electrode connected to the first node.   
     
     
         12 . The scan driver of  claim 11 , wherein the fifth control transistor includes:
 a first electrode connected to the second control node;   a second electrode connected to the first voltage terminal; and   a third electrode connected to the second node, and   wherein the first capacitor is between the first electrode of the fifth control transistor and the third electrode of the fifth control transistor.   
     
     
         13 . The scan driver of  claim 1 , wherein the clock signal includes a first clock signal and a second clock signal having different phase from each other,
 wherein clock terminals of odd-numbered stages among the plurality of stages receive the first clock signal, and   wherein clock terminals of even-numbered stages among the plurality of stages receive the second clock signal.   
     
     
         14 . An electronic device comprising:
 a display panel including a pixel;   a data driver configured to output a data signal to the display panel; and   a scan driver including a plurality of stages sequentially connected to each other to output a scan signal to the display panel,   wherein each stage includes:   a first control transistor connected between a first input terminal and a first node, the first control transistor operating in response to a clock signal provided through a clock terminal;   a second control transistor connected between a second input terminal and a second node, the second control transistor operating in response to the clock signal;   a third control transistor connected between the first node and a first control node, the third control transistor operating in response to a first voltage provided through a first voltage terminal;   a fourth control transistor connected between a second voltage terminal and a second control node, the fourth control transistor operating in response to a potential at the first node;   a fifth control transistor electrically connected between the second control node and the first voltage terminal, the fifth control transistor operating in response to a potential at the second node;   a first capacitor connected between the second node and the second control node; and   an output circuit configured to output a scan signal in response to a potential at the first control node and a potential at the second control node.   
     
     
         15 . The electronic device of  claim 14 , wherein the second control node of each of the stages is connected to a carry terminal, and
 wherein the carry terminal outputs the potential at the second control node as a carry signal.   
     
     
         16 . The electronic device of  claim 15 , wherein the carry terminal is connected to the second input terminal of a next stage. 
     
     
         17 . The electronic device of  claim 15 , wherein a potential difference between the second node and the second control node is substantially maintained at zero during a deactivation period of the second node. 
     
     
         18 . The electronic device of  claim 15 , wherein the output circuit includes:
 a first output transistor connected between an output terminal and the first voltage terminal, the first output transistor operating in response to the potential at the first control node; and   a second output transistor connected between the output terminal and the second voltage terminal, the second output transistor operating in response to the potential at the second control node.   
     
     
         19 . The electronic device of  claim 18 , wherein the output terminal is connected to the first input terminal of a next stage. 
     
     
         20 . The electronic device of  claim 19 , wherein the first input terminal of a first stage among the plurality of stages receives a first start signal as a previous scan signal, and
 wherein the second input terminal of the first stage receives a second start signal as a previous carry signal.