Memory device having segmented data line structure

Abstract

A memory device includes a plurality of sets of bitlines, a set of data lines and a column selection circuit. Each data line is segmented into line segments separated from each other. A first data line includes a first line segment and a second line segment adjacent to each other. A second data line includes a first line segment. The column selection circuit is configured to selectively a first bitline in a first set of bitlines and a first bitline in a second set of bitlines to the first line segment and the second line segment of the first data line, respectively, and to selectively couple a second bitline in the first set of bitlines and a second bitline in the second set of bitlines to the first line segment of the second data line.

What is claimed is: 
     
         1 . A memory device, comprising:
 a plurality of sets of bitlines, comprising a first set of bitlines and a second set of bitlines;   a set of data lines, each data line being segmented into a plurality of line segments separated from each other, the set of data lines comprising a first data line and a second data line, wherein the first data line comprises a first line segment and a second line segment adjacent to each other, and the second data line comprises a first line segment; and   a column selection circuit, configured to selectively couple a first bitline in the first set of bitlines and a first bitline in the second set of bitlines to the first line segment and the second line segment of the first data line, respectively, and to selectively couple a second bitline in the first set of bitlines and a second bitline in the second set of bitlines to the first line segment of the second data line,   wherein the first line segment and the second line segment of the first data line are arranged along a first direction, and the first data line and the second data line are spaced apart along a second direction orthogonal to the first direction.   
     
     
         2 . The memory device of  claim 1 , wherein the first data line is segmented into a first number of line segments, the second data line is segmented into a second number of line segments, and the second number is different from the first number. 
     
     
         3 . The memory device of  claim 1 , wherein the first data line is segmented into a first number of line segments, and the second data line is segmented into a second number of line segments; each of the first number and the second number is greater than two. 
     
     
         4 . The memory device of  claim 1 , wherein the column selection circuit is configured to select one set of bitlines from among the sets of bitlines; when the first set of bitlines is selected, the column selection circuit is configured to couple the first bitline in the first set of bitlines to the first line segment of the first data line to transmit a predetermined data bit; when the second set of bitlines is selected, the column selection circuit is configured to couple the first bitline in the second set of bitlines to the second line segment of the first data line to transmit the predetermined data bit. 
     
     
         5 . The memory device of  claim 1 , wherein the column selection circuit is configured to select one set of bitlines from among the sets of bitlines; when the first set of bitlines is selected, the column selection circuit is configured to couple the first bitline in the first set of bitlines to the first line segment of the first data line to transmit a predetermined data bit; when the second set of bitlines is selected, the column selection circuit is configured to couple a third bitline in the second set of bitlines to the first line segment of the first data line to transmit the predetermined data bit. 
     
     
         6 . The memory device of  claim 5 , wherein the first bitline in the first set of bitlines is arranged between the third bitline and the first bitline in the second set of bitlines. 
     
     
         7 . The memory device of  claim 1 , wherein the sets of bitlines further comprises a third set of bitlines, and the column selection circuit is configured to select one set of bitlines from among the set of bitlines; when the third set of bitlines is selected, the column selection circuit is further configured to couple a first bitline in the third set of bitlines to the second line segment of the first data line, and couple a second bitline in the third set of bitlines to a second line segment of the second data line adjacent to the first line segment of the second data line. 
     
     
         8 . The memory device of  claim 1 , wherein the column selection circuit is configured to select one set of bitlines from among the set of bitlines; when the first set of bitlines is selected, the column selection circuit is configured to couple a third bitline in the first set of bitlines to the second line segment of the first data line, and couple a fourth bitline in the first set of bitlines to a second line segment of the second data line adjacent to the first line segment of the second data line. 
     
     
         9 . The memory device of  claim 1 , wherein the column selection circuit is configured to select one set of bitlines from among the set of bitlines; when the second set of bitlines is selected, the column selection circuit is configured to couple a third bitline in the second set of bitlines to a third line segment of the first data line adjacent to the second line segment of the first data line, and couple a fourth bitline in the second set of bitlines to a second line segment of the second data line adjacent to the first line segment of the second data line. 
     
     
         10 . The memory device of  claim 9 , further comprising:
 a first multiplexer circuit, having a first output terminal, the first multiplexer circuit being configured to couple one of the first line segment and the second line segment of the first data line to the first output terminal according to whether the second set of bitlines is selected; and   a second multiplexer circuit, having a second output terminal, the second multiplexer circuit being configured to couple one of the second line segment and the third line segment of the first data line to the second output terminal according to whether the second set of bitlines is selected.   
     
     
         11 . The memory device of  claim 10 , further comprising:
 a first semiconductor substrate and a second semiconductor substrate stacked one above other, wherein the set of data lines is formed on the first semiconductor substrate, and the first multiplexer circuit and the second multiplexer circuit are formed on the second semiconductor substrate.   
     
     
         12 . The memory device of  claim 10 , wherein the first output terminal of the first multiplexer circuit and the second output terminal of the second multiplexer circuit form a first data width, the second data line forms a second data width, and the first data width is equal to the second data width. 
     
     
         13 . A memory device, comprising:
 a first bitline group and a second bitline group, each bitline group comprising a plurality of sets of bitlines;   a first data line, segmented into a plurality of line segments separated from each other, the first data line being arranged to transmit a first set of data bits;   a second data line, segmented into a plurality of line segments separated from each other, the second data line being arranged to transmit a second set of data bits; and   a column selection circuit, configured to selectively couple the sets of bitlines in the first bitline group to a first line segment and a second line segment of the first data line, and to a first line segment of the second data line; the column selection circuit being further configured to selectively couple the sets of bitlines in the second bitline group to the second line segment and a third line segment of the first data line, and to a second line segment of the second data line,   wherein the plurality of line segments of the first data line are arranged along a first direction, the plurality of line segments of the second data line are arranged along the first direction, and the first data line and the second data line are spaced apart along a second direction orthogonal to the first direction.   
     
     
         14 . The memory device of  claim 13 , wherein the column selection circuit is arranged to select one set of bitlines from among the plurality of sets of bitlines in each bitline group, and to couple the selected set of bitlines to the first data line and the second data line;
 when a first set of bitlines in each bitline group is selected, a first bitline and a second bitline in the first set of bitlines in the first bitline group are coupled to the first line segment of the first data line and the first line segment of the second data line to transmit a first data bit in the first set of data bits and a first data bit in the second set of data bits, respectively, and a first bitline and a second bitline in the first set of bitlines in the second bitline group are coupled to the second line segment of the first data line and the second line segment of the second data line to transmit a second data bit in the first set of data bits and a second data bit in the second set of data bits, respectively; and   when a second set of bitlines in each group of bitlines is selected, a first bitline and a second bitline in the second set of bitlines in the first bitline group are coupled to the second line segment of the first data line and the first line segment of the second data line to transmit the first data bit in the first set of data bits and the first data bit in the second set of data bits, respectively, and a first bitline and a second bitline in the second set of bitlines in the second bitline group are coupled to the third line segment of the first data line and the second line segment of the second data line to transmit the second data bit in the first set of data bits and the second data bit in the second set of data bits, respectively.   
     
     
         15 . The memory device of  claim 13 , further comprising:
 a first multiplexer circuit, having a first output terminal, the first multiplexer circuit being configured to output a first data bit in the first set of data bits by coupling one of the first line segment and the second line segment of the first data line to the first output terminal; and   a second multiplexer circuit, having a second output terminal, the second multiplexer circuit being configured to output a second data bit in the first set of data bits by coupling one of the second line segment and the third line segment of the first data line to the second output terminal.   
     
     
         16 . The memory device of  claim 15 , wherein the column selection circuit is arranged to select one set of bitlines from among the plurality of sets of bitlines in each bitline group, and to couple the selected set of bitlines to the first data line and the second data line;
 when a predetermined set of bitlines in each bitline group is unselected, the first multiplexer circuit is configured to couple the first line segment of the first data line to the first output terminal, and the second multiplexer circuit is configured to couple the second line segment of the first data line to the second output terminal; and   when the predetermined set of bitlines in each bitline group is selected, the first multiplexer circuit is configured to couple the second line segment of the first data line to the first output terminal, and the second multiplexer circuit is configured to couple the third line segment of the first data line to the second output terminal.   
     
     
         17 . The memory device of  claim 15 , further comprising:
 a first semiconductor substrate and a second semiconductor substrate stacked one above other, wherein the first data line is formed on the first semiconductor substrate, and each of the first multiplexer circuit and the second multiplexer circuit is formed on the second semiconductor substrate.   
     
     
         18 . A memory device, comprising:
 a plurality of sets of bitlines, comprising a first set of bitlines and a second set of bitlines;   a first data line and a second data line, each data line being segmented into a plurality of line segments separated from each other; and   a column selection circuit, configured to selectively couple a first bitline in the first set of bitlines and a first bitline in the second set of bitlines to a first line segment of the first data line, and to selectively couple a second bitline in the first set of bitlines and a second bitline in the second set of bitlines to a first line segment of the second data line; the first set of bitlines being arranged between the first bitline and the second bitline in the second set of bitlines.   
     
     
         19 . The memory device of  claim 18 , wherein the column selection circuit is arranged to select one set of bitlines from among the sets of bitlines, and to couple the selected set of bitlines to the first data line and the second data line; when the second set of bitlines is selected, the column selection circuit is configured to couple a third bitline and a fourth bitline in the second set of bitlines to a second line segment of the first data line and a second line segment of the second data line, respectively; the third bitline and the second bitline in the second set of bitlines are adjacent to each other. 
     
     
         20 . The memory device of  claim 19 , wherein the second bitline in the second set of bitlines is further adjacent to the second bitline in the first set of bitlines, and arranged between the second bitline in the first set of bitlines and the third bitline in the second set of bitlines.