3D semiconductor memory device including inter-finger structure and interlayer insulating layers configured to absorb compressing stress

Abstract

A semiconductor memory device includes: a stacked structure including first layers including conductive layers disposed in a first and a third regions and insulating layers disposed in a second region, first to third insulating members extending in a stacking direction, semiconductor layers disposed in the first and the third regions, and a contact electrode disposed in the second region. The first and the third insulating members extend across the first to third regions and the second insulating member extends across the first and the third regions. The second insulating member contacts the insulating layers. The first layers extend in a direction in the second region from a side of the first insulating member to a side of the third insulating member. The conductive layers in the first and the third regions are mutually connected via conductive layers in the second region.

What is claimed is: 
     
         1 . A semiconductor memory device comprising:
 a semiconductor substrate including a first region, a second region, and a third region arranged in a first direction, the second region being disposed between the first region and the third region in the first direction;   a stacked structure disposed above the semiconductor substrate and including a plurality of first layers stacked so as to be spaced apart from one another, the plurality of first layers including a plurality of conductive layers disposed corresponding to the respective plurality of first layers in the first region and the third region, the stacked structure including a plurality of insulating layers disposed corresponding to the respective plurality of first layers in the second region;   first to third insulating members disposed above the semiconductor substrate and extending in the first direction and in a stacking direction of the plurality of first layers in the stacked structure, the second insulating member being disposed so as to be spaced apart from the first insulating member and the third insulating member in a second direction intersecting with the first direction and the stacking direction between the first insulating member and the third insulating member in the second direction, the first insulating member and the third insulating member extending across the first to third regions in the first direction and separating the plurality of first layers in the second direction, the second insulating member extending across the first region and the third region in the first direction; and   a plurality of semiconductor layers disposed extending in the stacking direction in the stacked structure in the first region and the third region, the plurality of semiconductor layers forming a plurality of memory cells in a plurality of intersection portions with the plurality of conductive layers, wherein   the second insulating member contacts side edge portions on both sides of the plurality of insulating layers in the first direction in the second region,   the plurality of first layers extend in the second direction in the second region from an edge portion on a side of the first insulating member through a central region including the plurality of insulating layers to an edge portion on a side of the third insulating member, the plurality of first layers including the plurality of conductive layers in each of a first side region in the second direction between the first insulating member and the central region and a second side region in the second direction between the third insulating member and the central region,   the plurality of conductive layers in the first region and the plurality of conductive layers in the third region are mutually connected via the plurality of conductive layers in the first side region and the second side region, and   the second insulating member includes:
 a first part extending in the first direction in the first region; and 
 a second part partially extending in the second direction along one side edge portion on a first region side of the side edge portions of the insulating layers in the second region, the second part directly contacts the first part. 
   
     
     
         2 . The semiconductor memory device according to  claim 1 , wherein
 the second part has a length in the first direction smaller than a length of the first part in the second direction.   
     
     
         3 . The semiconductor memory device according to  claim 1 , wherein
 the second part has a length in the second direction that is equal to or more than a half a first length, the first length being a distance between the first insulating member and the second insulating member in the second direction in the first region.   
     
     
         4 . The semiconductor memory device according to  claim 1 , wherein
 the plurality of conductive layers in the first side region in the second region directly contact the plurality of insulating layers, and   the plurality of conductive layers in the second side region in the second region directly contact the plurality of insulating layers.   
     
     
         5 . The semiconductor memory device according to  claim 1 , wherein
 the plurality of first layers extend in the second direction in the second region continuously from the edge portion on the side of the first insulating member to the edge portion on the side of the third insulating member.   
     
     
         6 . A semiconductor memory device comprising:
 a semiconductor substrate including a first region, a second region, and a third region arranged in a first direction, the second region being disposed between the first region and the third region in the first direction;   a stacked structure disposed above the semiconductor substrate and including a plurality of first layers and a plurality of interlayer insulating layers alternately stacked, the plurality of first layers including a plurality of conductive layers disposed corresponding to the respective plurality of first layers in the first region and the third region, the stacked structure including a plurality of insulating layers disposed corresponding to the respective plurality of first layers in the second region;   first to third insulating members disposed above the semiconductor substrate and extending in the first direction and in a stacking direction of the stacked structure of the plurality of first layers and the plurality of interlayer insulating layers in the stacked structure, the second insulating member being disposed so as to be spaced apart from the first insulating member and the third insulating member in a second direction intersecting with the first direction and the stacking direction between the first insulating member and the third insulating member in the second direction, the first insulating member and the third insulating member extending across the first to third regions in the first direction and separating the plurality of first layers and the plurality of interlayer insulating layers in the second direction, the second insulating member extending across the first region and the third region in the first direction; and   a plurality of semiconductor layers disposed extending in the stacking direction in the stacked structure in the first region and the third region, the plurality of semiconductor layers forming a plurality of memory cells in a plurality of intersection portions with the plurality of conductive layers, wherein
 the second insulating member contacts side edge portions on both sides of the plurality of insulating layers in the first direction in the second region, 
   the plurality of first layers include the plurality of conductive layers in the second region in each of a first side region in the second direction between the first insulating member and a central region including the plurality of insulating layers and a second side region in the second direction between the third insulating member and the central region, the plurality of conductive layers in the first region and the plurality of conductive layers in the third region are mutually connected via the plurality of conductive layers in the first side region and the second side region,   the plurality of interlayer insulating layers extend from an edge portion on a side of the first insulating member to an edge portion on a side of the third insulating member through the central region in the second direction in the second region, and   the second insulating member includes:
 a first part extending in the first direction in the first region; and 
 a second part partially extending in the second direction along one side edge portion on a first region side of the side edge portions of the insulating layers in the second region, the second part directly contacting the first part. 
   
     
     
         7 . The semiconductor memory device according to  claim 6 , wherein
 the second part has a length in the first direction smaller than a length of the first part in the second direction.   
     
     
         8 . The semiconductor memory device according to  claim 6 , wherein
 the second part has a length in the second direction that is equal to or more than a half a first length, the first length being a distance between the first insulating member and the second insulating member in the second direction in the first region.   
     
     
         9 . The semiconductor memory device according to  claim 6 , wherein
 the plurality of conductive layers in the first side region in the second region directly contact the plurality of insulating layers, and   the plurality of conductive layers in the second side region in the second region directly contact the plurality of insulating layers.   
     
     
         10 . The semiconductor memory device according to  claim 6 , wherein
 the plurality of interlayer insulating layers extend continuously from the edge portion on the side of the first insulating member to the edge portion on the side of the third insulating member in the second direction in the second region.   
     
     
         11 . A semiconductor memory device comprising:
 a semiconductor substrate; and   a memory cell array, wherein the semiconductor substrate includes a first region and a second region arranged in a first direction,   the memory cell array includes:
 a first finger structure and a second finger structure extending across the first region and the second region in the first direction and arranged in a second direction intersecting with the first direction; and 
 an inter-finger structure disposed between the first finger structure and the second finger structure and extending across the first region and the second region in the first direction, 
   the first finger structure includes:
 a plurality of first conductive layers arranged in a third direction intersecting with a substrate surface of the semiconductor substrate; and 
 a first semiconductor layer disposed in the first region, and extending in the third direction through the plurality of first conductive layers, 
   the second finger structure includes:
 a plurality of second conductive layers arranged in the third direction; and 
 a second semiconductor layer disposed in the first region, and extending in the third direction, and opposed to through the plurality of second conductive layers, 
   the inter-finger structure includes:
 a plurality of first insulating layers disposed in the second region and arranged in the third direction; and 
 a second insulating layer extending in the third direction and being in contact with a side edge portion on one side in the first direction of the plurality of first insulating layers in the second region, 
   the plurality of first insulating layers have side surfaces on one side in the second direction, and the side surfaces on the one side contact the plurality of first conductive layers, and   the plurality of first insulating layers have side surfaces on a second side opposite to the first side in the second direction, and the side surfaces on the second side contact the plurality of second conductive layers, and   the second insulating layer includes:
 a first part extending in the first direction in the first region; and 
 a second part partially extending in the second direction along the side edge portion on the one side in the first direction of the plurality of first insulating layers in the second region, the second part directly contacting the first part. 
   
     
     
         12 . The semiconductor memory device according to  claim 11 , wherein
 each of the plurality of first insulating layers include:
 a third insulating layer; 
 a first high dielectric constant insulating layer disposed on side surfaces on the first side in the second direction of the third insulating layer; and 
 a second high dielectric constant insulating layer disposed on a side surface on the second side in the second direction of the third insulating layer, 
   the first high dielectric constant insulating layer contacts one of the plurality of first conductive layers in the second direction, and   the second high dielectric constant insulating layer contacts one of the plurality of second conductive layers in the second direction.