Memory controller and memory system including the same

Abstract

A memory system, a memory controller are provided. The memory system includes: a memory device; and a memory controller configured to: control a patrol scrubbing operation in which data is read from and re-written to the memory device, based on a scrubbing cycle; and adaptively adjust the scrubbing cycle based on a comparison of an error count value of the memory device and a plurality of risk threshold values.

What is claimed is: 
     
         1 . A memory system comprising:
 a memory device; and   a memory controller configured to:
 control a patrol scrubbing operation in which data is read from and re-written to the memory device, based on a scrubbing cycle; 
 compare an error count value of the memory device with a plurality of risk threshold values to identify a range, from among a plurality of ranges, comprising the error count value; and 
 set the scrubbing cycle to an updated scrubbing cycle, from among a plurality of scrubbing cycles, that is associated with the range, 
   wherein the plurality of scrubbing cycles comprise a first scrubbing cycle associated with a first range between zero and a first risk threshold value, and a second scrubbing cycle associated with a second range between the first risk threshold value and a second risk threshold value.   
     
     
         2 . The memory system of  claim 1 , wherein the error count value indicates a number of correctable errors that have occurred in the memory device. 
     
     
         3 . The memory system of  claim 2 , wherein the memory controller is further configured to:
 increase the error count value based on a correctable error being detected by the patrol scrubbing operation;   identify an address of a memory cell in which the correctable error has been detected; and   update fail information based on the error count value and the address.   
     
     
         4 . The memory system of  claim 3 , wherein the memory controller is further configured to control the patrol scrubbing operation to be performed for memory cells adjacent to the address. 
     
     
         5 . The memory system of  claim 1 , wherein the plurality of scrubbing cycles are stored as register bits, and
 wherein the register bits indicate the plurality of risk threshold values.   
     
     
         6 . The memory system of  claim 1 , wherein the plurality of scrubbing cycles are stored as register bits,
 wherein the register bits indicate the first scrubbing cycle associated with the first range and the second scrubbing cycle associated with the second range,   wherein the second scrubbing cycle is shorter than the first scrubbing cycle, and   wherein the memory controller further configured to set the scrubbing cycle to:
 the first scrubbing cycle based on the first range comprising the error count value; and 
 the second scrubbing cycle based on the second range comprising the error count value. 
   
     
     
         7 . The memory system of  claim 1 , wherein the memory controller is further configured to, based on the memory device being in an active state, control the patrol scrubbing operation to be performed at the scrubbing cycle. 
     
     
         8 . The memory system of  claim 7 , wherein the memory controller is further configured to, based on the memory device being in an idle state, perform the patrol scrubbing operation at a preset idle scrubbing cycle. 
     
     
         9 . A memory system comprising:
 a plurality of memory devices; and   a memory controller configured to identify a risk level based on fail information of the plurality of memory devices, identify a scrubbing cycle, from among a plurality of scrubbing cycles, that is associated with the risk level, and control a patrol scrubbing operation to be performed at the scrubbing cycle,   wherein the plurality of scrubbing cycles comprise a first scrubbing cycle associated with a first range between zero and a first risk threshold value, and a second scrubbing cycle associated with a second range between the first risk threshold value and a second risk threshold value.   
     
     
         10 . The memory system of  claim 9 , wherein the memory controller is further configured to control the patrol scrubbing operation to be performed at the scrubbing cycle or an idle scrubbing cycle based on an operation state of the plurality of memory devices. 
     
     
         11 . The memory system of  claim 10 , wherein the memory controller is further configured to perform the patrol scrubbing operation at least two times within a set time period based on the plurality of memory devices being in an idle state. 
     
     
         12 . The memory system of  claim 9 , wherein the memory controller is further configured to:
 read data from each of the plurality of memory devices;   increase an error count value based on a correctable error being detected in the data read from the plurality of memory devices; and   update the fail information based on the error count value and an address of a memory cell corresponding to the correctable error.   
     
     
         13 . The memory system of  claim 12 , wherein the plurality of scrubbing cycles are stored as register bits, and
 wherein the register bits indicate a first risk level associated with the first range and a second risk level associated with the second range, and   wherein the memory controller is further configured to:
 identify the risk level as the first risk level based on the first range comprising the error count value; and 
 identify the risk level as the second risk level based on the second range comprising the error count value. 
   
     
     
         14 . The memory system of  claim 13 , wherein the memory controller is further configured to:
 set the scrubbing cycle to the first scrubbing cycle based on the first range comprising the error count value; and   set the scrubbing cycle to the second scrubbing cycle based on the second range comprising the error count value.   
     
     
         15 . The memory system of  claim 12 , wherein the memory controller is further configured to control the patrol scrubbing operation for a memory chip corresponding to the address at the scrubbing cycle. 
     
     
         16 . A memory controller comprising:
 a non-volatile memory storing fail information; and   a processor configured to control:
 a scrubbing cycle, from among a plurality of scrubbing cycles, to be set based on the fail information; and 
 an Error Correction Code (ECC) engine to perform a scrubbing operation in which a bit error of data read from a memory device is detected and corrected, and corrected data is written in the memory device, at the scrubbing cycle, 
   wherein the plurality of scrubbing cycles comprise a first scrubbing cycle associated with a first range between zero and a first risk threshold value, and a second scrubbing cycle associated with a second range between the first risk threshold value and a second risk threshold value.   
     
     
         17 . The memory controller of  claim 16 , wherein the processor is further configured to:
 increase an error count value based on the bit error being detected; and   update the fail information based on increase of the error count value.   
     
     
         18 . The memory controller of  claim 17 , wherein the plurality of scrubbing cycles are stored as register bits,
 wherein the register bits indicate a first risk level associated with the first range and a second risk level associated with the second range, and   wherein the processor is further configured to:
 identify a risk level as the first risk level based on the first range comprising the error count value; 
 identify the risk level as the second risk level based on the second range comprising the error count value; and 
 set the scrubbing cycle corresponding to the risk level. 
   
     
     
         19 . The memory controller of  claim 18 , wherein the register bits indicate a plurality of risk threshold values, and a plurality of risk levels,
 wherein the plurality of risk threshold values comprise the first risk threshold value and the second risk threshold value, and   wherein the plurality of risk levels comprise the first risk level and the second risk level.   
     
     
         20 . The memory controller of  claim 17 , wherein the fail information indicates an address of a memory cell in which the bit error is detected.