Backside contacts for signal routing

Abstract

A cell layout that may be implemented in FinFET devices or other FET devices is disclosed. The cell layout utilizes an isolation gate structure to provide routing between a signal input of an active gate and a backside metal layer. The isolation gate structure includes a metal fill surrounded by gate spacers. The metal fill connects between the topside layers in the device and the backside layer in the device. The metal fill may be connected to the signal input of the active gate through routing either in a topside metal layer or a metal wire placed in a topside insulating layer. The isolation gate structure can be part of any standard cell being placed at a cell boundary or inside the cell to provide access to backside signal routing. Additionally, filler cells with isolation gate structures may provide backside routing connections for adjacent functional cells.

What is claimed is: 
     
         1 . An apparatus, comprising:
 a transistor formed in a transistor region of an integrated circuit, the transistor having an active gate with a signal input;   a metal layer located below the transistor region in a vertical dimension perpendicular to the transistor region;   a gate structure formed in the transistor region of the integrated circuit, the gate structure including a metal fill positioned between gate spacers in the transistor region, wherein the gate structure is positioned on a first side of the transistor in a horizontal dimension perpendicular to the vertical dimension, and wherein the metal fill is connected to the metal layer; and   a metal wire located above the transistor region in the vertical dimension, wherein the metal wire connects the metal fill to the signal input of the active gate.   
     
     
         2 . The apparatus of  claim 1 , further comprising an upper metal layer located above the transistor region in the vertical dimension, wherein the metal wire is positioned in the upper metal layer. 
     
     
         3 . The apparatus of  claim 1 , further comprising:
 an upper metal layer located above the transistor region in the vertical dimension; and   an insulation layer positioned between the transistor region and the upper metal layer, wherein the metal wire is positioned in the insulation layer.   
     
     
         4 . The apparatus of  claim 1 , wherein the metal fill and the gate spacers in the gate structure extend below the transistor in the vertical dimension, and wherein the metal fill in the gate structure is separated from the first side of the transistor by at least one of the gate spacers to provide electrical isolation between the metal fill and the active gate. 
     
     
         5 . The apparatus of  claim 1 , further comprising a second gate structure formed in the transistor region of the integrated circuit, the second gate structure including a second metal fill positioned between second gate spacers in the transistor region, wherein the second gate structure is positioned on a second side of the transistor in the horizontal dimension, the second side being on an opposite side of the first side of the transistor in the horizontal dimension. 
     
     
         6 . The apparatus of  claim 1 , further comprising a control signal routed to the signal input of the active gate, wherein the control signal is routed from the metal layer to the signal input through the metal fill and the metal wire. 
     
     
         7 . The apparatus of  claim 1 , further comprising a metal signal wire in the metal layer, wherein the metal fill connects the signal input of the active gate to the metal signal wire. 
     
     
         8 . The apparatus of  claim 7 , wherein the metal signal wire is connected to at least one additional transistor formed in the transistor region of the integrated circuit. 
     
     
         9 . The apparatus of  claim 1 , further comprising:
 an insulation layer positioned between the transistor region and the metal layer; and   a gate contact via in the insulation layer, the gate contact via providing connection between the metal fill and the metal layer.   
     
     
         10 . An apparatus, comprising:
 a transistor formed in a transistor region of an integrated circuit;   a first metal layer located above the transistor region in a vertical dimension perpendicular to the transistor region;   a second metal layer located below the transistor region in the vertical dimension; and   a gate structure formed in the transistor region of the integrated circuit, the gate structure including a metal fill positioned between gate spacers in the transistor region, wherein the gate structure is positioned on a first side of the transistor in a horizontal dimension perpendicular to the vertical dimension, and wherein the metal fill connects the first metal layer and the second metal layer.   
     
     
         11 . The apparatus of  claim 10 , further comprising:
 an active gate in the transistor, the active gate having a signal input, wherein the signal input is connected to the metal fill through the first metal layer.   
     
     
         12 . The apparatus of  claim 10 , further comprising:
 an active gate in the transistor, the active gate having a signal input; and   a first metal wire located in the first metal layer, wherein the first metal wire connects the signal input to the metal fill.   
     
     
         13 . The apparatus of  claim 12 , further comprising:
 a second metal wire located in the second metal layer;   wherein the second metal wire is connected to the signal input through the metal fill and the first metal wire.   
     
     
         14 . The apparatus of  claim 10 , wherein the transistor and the gate structure are positioned in a filler cell, the transistor in the transistor region of the filler cell being inactive, the apparatus further comprising:
 a functional cell positioned adjacent to the filler cell, wherein the functional cell includes an active transistor having an active gate with a signal input, wherein the signal input of the active transistor is coupled to the first metal layer, and wherein the second metal layer provides routing for a control signal between the signal input and a backside metal layer of the functional cell.   
     
     
         15 . The apparatus of  claim 10 , further comprising:
 an insulation layer positioned between the transistor region and the first metal layer;   a first gate contact via in the insulation layer, the first gate contact via connecting the metal fill and the first metal layer, and   a second gate contact via in the insulation layer, the second gate contact via connecting a signal input of an active gate in the transistor and the first metal layer.   
     
     
         16 . An apparatus, comprising:
 a transistor formed in a transistor region of an integrated circuit;   a first insulation layer located above the transistor region in a vertical dimension perpendicular to the transistor region;   a metal layer located below the transistor region in the vertical dimension;   a second insulation layer located between the transistor region and the metal layer in the vertical dimension;   a gate structure formed in the transistor region of the integrated circuit, the gate structure including a metal fill positioned between gate spacers in the transistor region, wherein the gate structure is positioned on a first side of the transistor in a horizontal dimension perpendicular to the vertical dimension;   a metal wire positioned in the first insulation layer, wherein the metal wire is connected to the metal fill; and   a gate contact via positioned in the second insulation layer, wherein the gate contact via connects the metal fill to the metal layer.   
     
     
         17 . The apparatus of  claim 16 , further comprising an active gate in the transistor, wherein a signal input of the active gate is connected to the metal layer by the metal wire the metal fill, and the gate contact via. 
     
     
         18 . The apparatus of  claim 17 , wherein a source/drain region of the active gate is connected to the metal wire. 
     
     
         19 . The apparatus of  claim 17 , further comprising:
 a first gate contact via in the first insulation layer, the first gate contact via connecting the metal fill and the metal wire; and   a second gate contact via in the first insulation layer, the second gate contact via connecting the signal input of the active gate and the metal wire.   
     
     
         20 . The apparatus of  claim 16 , further comprising an upper metal layer located above the transistor region, wherein the upper metal layer is electrically isolated from the metal wire.