Semiconductor device layout structure, method for forming same, and test system

Abstract

Embodiments relate to the field of semiconductor, and disclose a semiconductor device layout structure, a method for forming the same, and a test system. The semiconductor device layout structure includes: an active layout layer including active pattern regions arranged along a first direction; device layout sublayers, where each of the device layout sublayer includes a gate pattern region; and a plurality of contact plug sets, where each of the contact plug sets includes a source contact plug and a drain contact plug. Along the first direction, in adjacent two gate pattern regions of the device layout sublayers, a pitch between the latter gate pattern region and the corresponding source contact plug and/or the drain contact plug and a pitch between the former gate pattern region and the corresponding source contact plug and/or the drain contact plug form an arithmetic progression.

What is claimed is: 
     
         1 . A semiconductor device layout structure, comprising:
 an active layout layer provided in a substrate, the active layout layer comprising a plurality of active pattern regions, wherein an arrangement direction of the plurality of active pattern regions forms a first direction;   a plurality of device layout sublayers, wherein each of the plurality of device layout sublayer is positioned on a side of a corresponding one of the plurality of active pattern regions facing away from the substrate, and each of the plurality of device layout sublayer comprises a gate pattern region, a source pattern region, and a drain pattern region; and   a plurality of contact plug sets, wherein each of the plurality of contact plug sets is positioned on a side of a corresponding one of the plurality of device layout sublayers facing away from the substrate, and each of the plurality of contact plug sets comprises a source contact plug and a drain contact plug, the source contact plug being connected to the source pattern region, the drain contact plug being connected to the drain pattern region, and along the first direction, a pitch between the source contact plug and the drain contact plug being a fixed value;   along the first direction, the gate pattern region in each of the plurality of device layout sublayers is positioned between the corresponding source contact plug and the corresponding drain contact plug; and along the first direction, in adjacent two of the plurality of device layout sublayers, a pitch between the latter gate pattern region and the corresponding source contact plug and a pitch between the former gate pattern region and the corresponding source contact plug forms an increasing arithmetic progression, and/or, in the adjacent two of the plurality of device layout sublayers, a pitch between the latter gate pattern region and the corresponding drain contact plug and a pitch between the former gate pattern region and the corresponding drain contact plug forms a decreasing arithmetic progression.   
     
     
         2 . The semiconductor device layout structure according to  claim 1 , wherein along the first direction, the gate pattern regions in the adjacent two of the plurality of device layout sublayers have an equal critical dimension. 
     
     
         3 . The semiconductor device layout structure according to  claim 1 , wherein each of the plurality of contact plug sets further comprises the gate contact plug, the gate contact plug being connected to the gate pattern region. 
     
     
         4 . The semiconductor device layout structure according to  claim 3 , wherein in each of the plurality of device layout sublayers, a vertical projection of at least part of the gate pattern region on the substrate is positioned outside a vertical projection of the active pattern region on the substrate. 
     
     
         5 . The semiconductor device layout structure according to  claim 4 , wherein a vertical projection of the gate contact plug on the substrate is positioned outside a vertical projection of the corresponding active pattern region on the substrate. 
     
     
         6 . The semiconductor device layout structure according to  claim 3 , further comprising a plurality of test groups, wherein each of the plurality of test groups is provided on a side of a corresponding one of the plurality of contact plug sets facing away from the substrate, and each of the plurality of test groups is connected to the corresponding one of the plurality of contact plug sets; and each of the plurality of test groups comprises a gate test terminal, a source test terminal, and a drain test terminal,
 wherein the gate test terminal is connected to the gate contact plug;   wherein the source test terminal is connected to the source contact plug; and   wherein the drain test terminal is connected to the drain contact plug.   
     
     
         7 . The semiconductor device layout structure according to  claim 6 , wherein the gate contact plugs in the plurality of contact plug sets are connected to the same gate test terminal. 
     
     
         8 . The semiconductor device layout structure according to  claim 7 , further comprising a plurality of connection pattern groups, wherein each of the plurality of connection pattern groups is provided on a side of a corresponding one of the plurality of contact plug sets facing away from the substrate, and each of the plurality of connection pattern groups connects the corresponding one of the plurality of contact plug sets with a corresponding one of the plurality of test groups; and each of the plurality of connection pattern groups comprises a first connection pattern region, a second connection pattern region, and a third connection pattern region,
 wherein the first connection pattern region connects the source contact plug with the source test terminal;   wherein the second connection pattern region connects the drain contact plug with the drain test terminal; and   wherein the third connection pattern region connects the gate contact plug with the gate test terminal.   
     
     
         9 . A test system, comprising the semiconductor device layout structure according to  claim 1 . 
     
     
         10 . The test system according to  claim 9 , wherein there are a plurality of semiconductor device layout structures in the test system; and among the plurality of semiconductor device layout structures, the gate pattern regions in adjacent two of the plurality of semiconductor device layout structures have different critical dimensions.