US12525547B2ActiveUtilityA1

Semiconductor package and method for manufacturing same

44
Assignee: NEPES CO LTDPriority: Mar 29, 2019Filed: Mar 24, 2020Granted: Jan 13, 2026
Est. expiryMar 29, 2039(~12.7 yrs left)· nominal 20-yr term from priority
H10W 90/722H10W 72/0198H10W 72/952H10W 72/9415H10W 72/942H10W 72/922H10W 72/29H10W 72/9413H10W 70/60H10W 70/6528H10W 90/00H10W 74/117H10W 70/685H10W 70/614H10W 70/611H10W 70/65H10W 70/09H10W 70/05H10W 72/072H10W 90/724H10W 72/252H10W 72/241H10W 40/25H10W 40/22H10W 42/121H10W 90/701H01L 2924/3511H01L 2225/1058H01L 2225/1035H01L 2224/214H01L 25/105H01L 24/20H01L 24/19H01L 23/5389H01L 23/5386H01L 23/5383H01L 23/3128H01L 21/4857H01L 23/562
44
PatentIndex Score
0
Cited by
25
References
3
Claims

Abstract

A semiconductor package, as a semiconductor package mounted on a circuit board, includes including: a body portion including a semiconductor chip, and a first surface and a second surface opposite to each other; and a structure including n insulating layers stacked on at least one of the first surface and the second surface of the body portion, wherein the semiconductor package has a predetermined target coefficient of thermal expansion (CTE), and the n insulating layers and the body portion have a thickness and a CTE satisfying a condition that an effective CTE of the semiconductor package becomes equal to the predetermined target CTE.

Claims

exact text as granted — not AI-modified
The invention claimed is: 
     
         1 . A method for manufacturing a semiconductor package, the method comprising:
 predetermining a target coefficient of thermal expansion (CTE) of the semiconductor package to correspond to a CTE of a circuit board on which the semiconductor package is to be mounted;   determining a thickness and a CTE of a body portion comprising a semiconductor chip;   determining a thickness and a CTE of each of n insulating layers (n is an integer greater than or equal to 2 and less than or equal to 100) for a structure comprising the n insulating layers stacked on at least one of a first surface and a second surface of the body portion, which are opposite to each other;   calculating an effective CTE of the semiconductor package corresponding to the determined thickness and the determined CTE of the body portion and the determined thickness and the determined CTE of each of the n insulating layers;   adjusting the determined thickness and the determined CTE of each of the n insulating layers under a condition that the effective CTE and the predetermined target CTE are the same while fixing the determined thickness and the determined CTE of the body portion; and   manufacturing the semiconductor package by performing a wafer level packaging process to have the determined thickness and the determined CTE of the body portion and the adjusted thickness and the adjusted CTE of each of the insulating layers of the structure,   wherein the effective CTE is calculated using Equation (1) below   
       
         
           
             
               
                 
                   
                     
                       effective 
                       ⁢ 
                           
                       CTE 
                     
                     = 
                     
                       
                         
                           A 
                           * 
                           B 
                         
                         + 
                         
                           ( 
                           
                             
                               C 
                               ⁢ 
                               1 
                               * 
                               D 
                               ⁢ 
                               1 
                             
                             + 
                             ⋯ 
                             + 
                             
                               Cn 
                               * 
                               Dn 
                             
                           
                           ) 
                         
                       
                       
                         A 
                         + 
                         
                           ( 
                           
                             
                               C 
                               ⁢ 
                               1 
                             
                             + 
                             ⋯ 
                             + 
                             Cn 
                           
                           ) 
                         
                       
                     
                   
                 
                 
                   
                     ( 
                     1 
                     ) 
                   
                 
               
             
           
         
         where A denotes the determined thickness of the body portion, B denotes the CTE of the body portion, Cn denotes the determined thickness of an nth insulating layer of the n insulating layers, and Dn denotes the determined a CTE of the nth insulating layer of the n insulating layers. 
       
     
     
         2 . The method of  claim 1 , wherein
 the adjusting of the determined CTE of each of the n insulating layers further comprises adjusting content of a filler contained in each of the n insulating layers to adjust the determined CTE of each of the n insulating layers, wherein the content of the filler is between 0 wt % and 88 wt %.   
     
     
         3 . The method of  claim 1 , wherein
 the adjusting of the determined CTE of each of the n insulating layers further comprises adjusting a size of a filler contained in each of the n insulating layers to adjust the determined CTE of each of the n insulating layers, wherein the size of the filler is greater than 0 micrometers and less than or equal to 10 micrometers.

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