Semiconductor structure with isolation region including combination of deep and shallow trench isolation structures and method

Abstract

Disclosed is a semiconductor structure and method of forming the semiconductor structure. Specifically, the semiconductor structure can include a first semiconductor fin extending from a semiconductor substrate. The semiconductor structure can further include an isolation region on the semiconductor substrate adjacent to a lower portion of the first semiconductor fin. The first semiconductor fin can, for example, be incorporated into a single-fin fin-type semiconductor device, such as a single-fin fin-type field effect transistor (FINFET). The isolation region can include at least one shallow trench isolation (STI) structure positioned laterally between and immediately adjacent to sections of a deep trench isolation (DTI) structure. With this alternating DTI-STI-DTI configuration, overall shrinkage of isolation material of the isolation region during anneals is reduced and, thus, so are stress-induced crystalline defects in the first semiconductor fin. Also disclosed are methods for forming such a semiconductor structure.

What is claimed is: 
     
         1 . A structure comprising:
 a semiconductor substrate;   a first semiconductor fin extending from the semiconductor substrate;   a second semiconductor fin extending from the semiconductor substrate, wherein the first semiconductor fin and the second semiconductor fin are in end-to-end alignment, and   an isolation region on the semiconductor substrate positioned laterally between adjacent ends of the first semiconductor fin and the second semiconductor fin,   wherein the isolation region includes at least one first isolation structure having a first height and a second isolation structure having a second height that is greater than the first height,   wherein the second isolation structure is in contact with the adjacent ends of the first semiconductor fin and the second semiconductor fin, and   wherein the first isolation structure is positioned laterally between and immediately adjacent to sections of the second isolation structure.   
     
     
         2 . The structure of  claim 1 ,
 wherein the semiconductor substrate has bottom surface,   wherein the first isolation structure has a first bottom immediately adjacent to the semiconductor substrate and a first top opposite the first bottom and the first height is measurable from the first bottom to the first top,   wherein the second isolation structure has a second bottom immediately adjacent to the semiconductor substrate and a second top opposite the second bottom and the second height is measurable from the second bottom to the second top, and   wherein the first bottom of the first isolation structure is separated from the bottom surface of the semiconductor substrate by a greater distance than the second bottom of the second isolation structure.   
     
     
         3 . The structure of  claim 1 , wherein the first isolation structure includes a first isolation material and wherein the second isolation structure includes a second isolation material that is different from the first isolation material. 
     
     
         4 . The structure of  claim 3 , wherein the first isolation material and the second isolation material have any of the following differences:
 the first isolation material and the second isolation material are different oxide materials, and   the first isolation material and the second isolation material have different carbon concentrations.   
     
     
         5 . The structure of  claim 1 , wherein the isolation region includes, between the first semiconductor fin and the second semiconductor fin, alternating first isolation structures having the first height and sections of the second isolation structure having the second height. 
     
     
         6 . The structure of  claim 1 , wherein the first isolation structure is surrounded on four sides by the second isolation structure. 
     
     
         7 . The structure of  claim 1 , wherein the first isolation structure is positioned laterally adjacent to a sidewall of a third semiconductor fin. 
     
     
         8 . A structure comprising:
 a semiconductor substrate;   a device including a first semiconductor fin extending from the semiconductor substrate;   a second semiconductor fin extending from the semiconductor substrate, wherein the first semiconductor fin and the second semiconductor fin are in end-to-end alignment; and   an isolation region on the semiconductor substrate positioned laterally between adjacent ends of the first semiconductor fin and the second semiconductor fin,   wherein the isolation region includes a first isolation structure having a first height and a second isolation structure having a second height that is greater than the first height,   wherein the second isolation structure is in contact with the adjacent ends of the first semiconductor fin and the second semiconductor fin, and   wherein the first isolation structure is positioned laterally between and immediately adjacent to sections of the second isolation structure.   
     
     
         9 . The structure of  claim 8 , wherein the device comprises a single-fin fin-type field effect transistor. 
     
     
         10 . The structure of  claim 8 ,
 wherein the semiconductor substrate has bottom surface,   wherein the first isolation structure has a first bottom immediately adjacent to the semiconductor substrate and a first top opposite the first bottom and the first height is measurable from the first bottom to the first top,   wherein the second isolation structure has a second bottom immediately adjacent to the semiconductor substrate and a second top opposite the second bottom and the second height is measurable from the second bottom to the second top, and   wherein the first bottom of the first isolation structure is separated from the bottom surface of the semiconductor substrate by a greater distance than the second bottom of the second isolation structure.   
     
     
         11 . The structure of  claim 8 , wherein the first isolation structure includes a first isolation material, and wherein the second isolation structure includes a second isolation material that is different from the first isolation material. 
     
     
         12 . The structure of  claim 8 , further including a second device including the second semiconductor fin. 
     
     
         13 . The structure of  claim 12 , wherein the isolation region includes, between the first semiconductor fin and the second semiconductor fin, alternating first isolation structures having the first height and sections of the second isolation structure having the second height. 
     
     
         14 . The structure of  claim 8 , wherein the first isolation structure is one of surrounded on four sides by the second isolation structure and positioned laterally immediately adjacent to a sidewall of a third semiconductor fin of a third device. 
     
     
         15 . A method including:
 forming a first semiconductor fin extending from a semiconductor substrate and a second semiconductor fin extending from the semiconductor substrate, wherein the first semiconductor fin and the second semiconductor fin are in end-to-end alignment; and   forming an isolation region on the semiconductor substrate positioned laterally between adjacent ends of the first semiconductor fin and the second semiconductor fin,   wherein the isolation region includes at least one first isolation structure having a first height and a second isolation structure having a second height that is greater than the first height,   wherein the second isolation structure is in contact with the adjacent ends of the first semiconductor fin and the second semiconductor fin, and   wherein the first isolation structure is positioned laterally between and immediately adjacent to sections of the second isolation structure.   
     
     
         16 . The method of  claim 15 , further comprising
 forming multiple semiconductor fins including the first semiconductor fin and the second semiconductor fin, wherein the forming of the isolation region includes:   filling spaces above the semiconductor substrate and between the multiple semiconductor fins with a first isolation material;   forming a mask layer above the multiple semiconductor fins and the first isolation material;   forming an opening in the mask layer to define a shape of the second isolation structure;   forming a trench extending through any semiconductor fin portion and the first isolation material aligned below the opening and further extending into the semiconductor substrate below the first isolation material; and   filling the trench with a second isolation material for the second isolation structure.   
     
     
         17 . The method of  claim 16 , wherein the first isolation material and the second isolation material have any of the following differences:
 the first isolation material and the second isolation material are different oxide materials, and   the first isolation material and the second isolation material have different carbon concentrations.   
     
     
         18 . The method of  claim 15 , wherein the forming of the isolation region includes forming the isolation region so that the first isolation structure is one of surrounded on four sides by the second isolation structure and positioned laterally immediately adjacent to a sidewall of a third semiconductor fin of the multiple semiconductor fins.