Pseudo main memory system

Abstract

A pseudo main memory system. The system includes a memory adapter circuit for performing memory augmentation using compression, deduplication, and/or error correction. The memory adapter circuit is connected to a memory, and employs the memory augmentation methods to increase the effective storage capacity of the memory. The memory adapter circuit is also connected to a memory bus and implements an NVDIMM-F or modified NVDIMM-F interface for connecting to the memory bus.

What is claimed is: 
     
         1 . A system comprising:
 a processor;   a memory system comprising:
 a processing circuit; and 
 a first memory; and 
   a second memory connected to the processor,   wherein the processing circuit is configured to store data in, and retrieve data from, the first memory   wherein the processing circuit is further configured to detect a first time threshold and output a first estimated ratio based on the first time threshold;   wherein the processing circuit is configured to detect a second time threshold and compute a second estimated ratio based on the second time threshold, wherein the second estimated ratio is computed as a function of one or more ratios stored in the first memory, and   wherein the processor is further configured to:
 maintain a cache in the second memory; 
 assess availability of space in the first memory based on the second estimated ratio; 
 identify a first instruction to evict first data stored in the cache; and 
 based on the first instruction to evict the first data, and based on assessing the availability of space in the first memory, store the first data in the first memory. 
   
     
     
         2 . The system of  claim 1 , wherein the first memory is modified according to the second estimated ratio based on at least one of:
 compression;   deduplication; and   error correction.   
     
     
         3 . The system of  claim 1 , wherein the processing circuit has a first interface connected to the processor and a second interface connected to the first memory. 
     
     
         4 . The system of  claim 3 , wherein the first interface is a second generation or higher generation double data rate synchronous dynamic random-access interface. 
     
     
         5 . The system of  claim 3 , wherein the second interface is a second generation or higher generation double data rate synchronous dynamic random-access interface. 
     
     
         6 . The system of  claim 3 , wherein the first interface is a non-volatile dual in-line memory module (NVDIMM-F) interface, and the system is configured to operate the memory system as a block device. 
     
     
         7 . The system of  claim 1 , wherein the first memory is a dynamic random-access memory and a second interface is a second generation or higher generation double data rate synchronous dynamic random-access memory interface. 
     
     
         8 . The system of  claim 1 , wherein the processing circuit is a single integrated circuit configured to perform at least one of:
 compression;   deduplication; and   error correction.   
     
     
         9 . The system of  claim 1 , wherein the processor is connected to the processing circuit and the second memory through a management module, and
 wherein the second memory is connected to the management module through a third interface, the third interface being a second generation or higher generation double data rate synchronous dynamic random-access memory interface.   
     
     
         10 . The system of  claim 1 , wherein the processor is configured to maintain a page cache in the second memory,
 wherein the processor is configured to call a cleancache function for clean pages in response to evicting the clean pages from the page cache, the cleancache function being configured to store the clean pages:
 in the first memory in response to sufficient space being available in the first memory; and 
 in persistent storage otherwise. 
   
     
     
         11 . The system of  claim 10 , wherein the cleancache function is configured to assess that the sufficient space is available in the first memory based on the second estimated ratio. 
     
     
         12 . The system of  claim 1 , wherein the processor is configured to maintain a user memory space in the second memory, and
 the processor is configured to call a frontswap function for dirty pages in response to evicting the dirty pages from the user memory space, the frontswap function being configured to store the dirty pages:
 in the first memory in response to sufficient space being available in the first memory; and 
 in persistent storage otherwise. 
   
     
     
         13 . The system of  claim 12 , wherein the frontswap function is configured to assess that the sufficient space is available in the first memory based on the second estimated ratio. 
     
     
         14 . The system of  claim 1 , wherein the processor is configured to:
 execute one or more applications, and   in response to an application of the one or more applications to a sysinfo function, return:
 a value for a total available memory based on a size of the first memory and a size of the second memory, and 
 a value for a total free memory based on an amount of free memory in the first memory and an amount of free memory in the second memory. 
   
     
     
         15 . The system of  claim 14 , wherein the value for the total free memory is a sum of the amount of free memory in the second memory, and
 a product of a minimum ratio and the amount of the free memory in the first memory, the minimum ratio being:
 the function of the one or more ratios stored in the first memory, and 
 a fixed ratio value otherwise. 
   
     
     
         16 . A method for operating a computer system that includes a processor, a memory system and a second memory connected to the processor, wherein the memory system includes a processing circuit and a first memory, the method comprising:
 storing data in, and retrieving data from, the first memory;   detecting a first time threshold;   outputting a first estimated ratio based on the first time threshold;   detecting a second time threshold;   computing, by the processing circuit, a second estimated ratio based on the second time threshold, wherein the second estimated ratio is computed as a function of one or more ratios stored in the first memory;   maintaining a cache in the second memory;   assessing, by the processor, availability of space in the first memory based on the second estimated ratio;   identifying a first instruction to evict first data stored in the cache; and   based on the first instruction to evict the first data, and based on assessing the availability of space in the first memory, storing the first data in the first memory.   
     
     
         17 . The method of  claim 16 , wherein the first memory is modified according to the second estimated ratio based on operation comprises at least one of:
 compression;   deduplication; and   error correction.   
     
     
         18 . The method of  claim 16 , comprising using the memory system as a block device operable with a non-volatile dual in-line memory module (NVDIMM-F) protocol. 
     
     
         19 . The method of  claim 16 , wherein the processing circuit is a single integrated circuit configured to perform at least one of:
 compression;   deduplication; and   error correction.   
     
     
         20 . A system comprising:
 a processor;   a memory system comprising:
 a first memory; and 
 memory adapter means for storing data in, and retrieving data from, the first memory, the memory adapter means being configured to output a first estimated ratio based on a first time threshold, the memory adapter means further being configured to compute a second estimated ratio based on a second time threshold, wherein the second estimated ratio is computed as a function of one or more ratios stored in the first memory, 
   the system being configured to operate the memory system as a block device,   wherein the system further comprises:
 a second memory connected to the processor, 
 wherein the processor is further configured to:
 maintain a cache in the second memory; 
 assess availability of space in the first memory based on the second estimated ratio; 
 identify a first instruction to evict first data stored in the cache; and 
 based on the first instruction to evict the first data, and based on assessing the availability of space in the first memory, store the first data in the first memory.