Host managed hotness data utilized for cache evictions and/or insertions

Abstract

Systems, apparatuses, and methods provide for a memory controller to manage cache evictions and/or insertions in a data server environment based at least in part on host managed hotness data. For example, a memory controller includes logic to receive a plurality of read and write requests from a host, where the plurality of read and write requests include an associated hotness data. A valid unit count of operational memory cells is maintained on a block-by-block basis for a plurality of memory blocks. A hotness index count is also maintained based at least in part on the hotness data on a block-by-block basis for the plurality of memory blocks. One or more memory blocks of the plurality of memory blocks are selected for eviction from a single level cell region to an x-level cell region based at least in part on the valid unit count and the hotness index count.

We claim: 
     
         1 . A semiconductor apparatus comprising:
 one or more substrates; and   logic coupled to the one or more substrates, wherein the logic is implemented at least partly in one or more of configurable or fixed-functionality hardware logic, the logic to:
 receive, via a memory controller of a memory device, a plurality of read and write requests from a host, wherein the plurality of read and write requests include an associated hotness data, 
 maintain, via the memory controller, a valid unit count, wherein the valid unit count comprises a count of valid operational memory cells on a block-by-block basis for a plurality of memory blocks, 
 maintain, via the memory controller, a hotness index count based at least in part on the hotness data, wherein the hotness index count is maintained on a block-by-block basis for the plurality of memory blocks, 
 determine, via the memory controller, a weighted composite value based at least in part on a valid unit weight value applied to the valid unit count and a hotness weight value applied to the hotness index count, and 
 select, via the memory controller, one or more memory blocks of the plurality of memory blocks for eviction based at least in part on the valid unit count, the hotness index count, and the weighted composite value, wherein the eviction is from a single level cell region to an x-level cell region. 
   
     
     
         2 . The semiconductor apparatus of  claim 1 , wherein the hotness data is based at least in part on a Last Recently Used list of repeat cache hits associated with the plurality of read and write requests and based at least in part on a type of data associated with the plurality of read and write requests. 
     
     
         3 . The semiconductor apparatus of  claim 1 , wherein the logic is further to:
 select, via the memory controller, at least one memory block of the plurality of memory blocks for insertion based at least in part on the hotness data, wherein the insertion is from the x-level cell region to the single level cell region.   
     
     
         4 . A semiconductor apparatus comprising:
 one or more substrates; and   logic coupled to the one or more substrates, wherein the logic is implemented at least partly in one or more of configurable or fixed-functionality hardware logic, the logic to:
 receive, via a memory controller of a memory device, a plurality of read and write requests from a host, wherein the plurality of read and write requests include an associated hotness data, 
 maintain, via the memory controller, a valid unit count, wherein the valid unit count comprises a count of valid operational memory cells on a block-by-block basis for a plurality of memory blocks, 
 maintain, via the memory controller, a hotness index count based at least in part on the hotness data, wherein the hotness index count is maintained on a block-by-block basis for the plurality of memory blocks, 
 determine, via the memory controller, a priority level from a plurality of priority levels for eviction based at least in part on the valid unit count and the hotness index count, wherein:
 one or more memory blocks of the plurality of memory blocks where the valid unit count is beneath a validity threshold and the hotness index count is beneath a hotness threshold are given a highest priority level for eviction from the plurality of priority levels; 
 one or more memory blocks of the plurality of memory blocks where the valid unit count is above the validity threshold and the hotness index count is above the hotness threshold are given a lowest priority level for eviction from the plurality of priority levels; 
 one or more memory blocks of the plurality of memory blocks where the valid unit count is above the validity threshold and the hotness index count is below the hotness threshold are given an intermediate priority level for eviction from the plurality of priority levels, wherein the intermediate priority level falls between the highest priority level and the lowest priority level; 
 one or more memory blocks of the plurality of memory blocks where the valid unit count is below the validity threshold and the hotness index count is above the hotness threshold are given a penultimate priority level for eviction from the plurality of priority levels, wherein the penultimate priority level falls between the intermediate priority level and the lowest priority level; and 
 
 select, via the memory controller, one or more memory blocks of the plurality of memory blocks for eviction based at least in part on the valid unit count, the hotness index count, and the priority level, wherein the eviction is from a single level cell region to an x-level cell region. 
   
     
     
         5 . A storage device comprising:
 a memory array including a single-level cell region and an x-level cell region; and   a memory controller coupled to the memory array, the memory controller to:
 receive, via the memory controller, a plurality of read and write requests from a host, wherein the plurality of read and write requests include an associated hotness data, 
 maintain, via the memory controller, a valid unit count, wherein the valid unit count comprises a count of valid operational memory cells on a block-by-block basis for a plurality of memory blocks, 
 maintain, via the memory controller, a hotness index count based at least in part on the hotness data, wherein the hotness index count is maintained on a block-by-block basis for the plurality of memory blocks, 
 determine, via the memory controller, a weighted composite value based at least in part on a valid unit weight value applied to the valid unit count and a hotness weight value applied to the hotness index count, and 
 select, via the memory controller, one or more memory blocks of the plurality of memory blocks for eviction based at least in part on the valid unit count, the hotness index count, and the weighted composite value, wherein the eviction is from a single level cell region to an x-level cell region. 
   
     
     
         6 . The storage device of  claim 5 , wherein the hotness data is based at least in part on a Last Recently Used list of repeat cache hits associated with the plurality of read and write requests and based at least in part on a type of data associated with the plurality of read and write requests. 
     
     
         7 . The storage device of  claim 5 , wherein the logic is further to:
 select, via the memory controller, at least one memory block of the plurality of memory blocks for insertion based at least in part on the hotness data, wherein the insertion is from the x-level cell region to the single level cell region.   
     
     
         8 . A storage device comprising:
 a memory array including a single-level cell region and an x-level cell region; and   a memory controller coupled to the memory array, the memory controller to:
 receive, via the memory controller, a plurality of read and write requests from a host, wherein the plurality of read and write requests include an associated hotness data, 
 maintain, via the memory controller, a valid unit count, wherein the valid unit count comprises a count of valid operational memory cells on a block-by-block basis for a plurality of memory blocks, 
 maintain, via the memory controller, a hotness index count based at least in part on the hotness data, wherein the hotness index count is maintained on a block-by-block basis for the plurality of memory blocks, 
 determine, via the memory controller, a priority level from a plurality of priority levels for eviction based at least in part on the valid unit count and the hotness index count, wherein:
 one or more memory blocks of the plurality of memory blocks where the valid unit count is beneath a validity threshold and the hotness index count is beneath a hotness threshold are given a highest priority level for eviction from the plurality of priority levels; 
 one or more memory blocks of the plurality of memory blocks where the valid unit count is above the validity threshold and the hotness index count is above the hotness threshold are given a lowest priority level for eviction from the plurality of priority levels; 
 one or more memory blocks of the plurality of memory blocks where the valid unit count is above the validity threshold and the hotness index count is below the hotness threshold are given an intermediate priority level for eviction from the plurality of priority levels, wherein the intermediate priority level falls between the highest priority level and the lowest priority level; 
 one or more memory blocks of the plurality of memory blocks where the valid unit count is below the validity threshold and the hotness index count is above the hotness threshold are given a penultimate priority level for eviction from the plurality of priority levels, wherein the penultimate priority level falls between the intermediate priority level and the lowest priority level; and 
 
 select, via the memory controller, one or more memory blocks of the plurality of memory blocks for eviction based at least in part on the valid unit count, the hotness index count, and the priority level, wherein the eviction is from a single level cell region to an x-level cell region. 
   
     
     
         9 . At least one non-transitory computer readable medium, comprising a set of instructions, which when executed by a computing device, cause the computing device to:
 receive, via a memory controller of a memory device, a plurality of read and write requests from a host, wherein the plurality of read and write requests include an associated hotness data;   maintain, via the memory controller, a valid unit count, wherein the valid unit count comprises a count of valid operational memory cells on a block-by-block basis for a plurality of memory blocks;   maintain, via the memory controller, a hotness index count based at least in part on the hotness data, wherein the hotness index count is maintained on a block-by-block basis for the plurality of memory blocks;   determine, via the memory controller, a weighted composite value based at least in part on a valid unit weight value applied to the valid unit count and a hotness weight value applied to the hotness index count; and   select, via the memory controller, one or more memory blocks of the plurality of memory blocks for eviction based at least in part on the valid unit count, the hotness index count, and the weighted composite value, wherein the eviction is from a single level cell region to an x-level cell region.   
     
     
         10 . The at least one non-transitory computer readable medium of  claim 9 , wherein the hotness data is based at least in part on a Last Recently Used list of repeat cache hits associated with the plurality of read and write requests and based at least in part on a type of data associated with the plurality of read and write requests. 
     
     
         11 . The at least one non-transitory computer readable medium of  claim 9 , wherein the set of instructions, which when executed by the computing device, cause the computing device further to:
 determine, via the memory controller, a priority level from a plurality of priority levels for eviction based at least in part on the valid unit count and the hotness index count, wherein the selection of the one or more memory blocks is based on the priority level.   
     
     
         12 . The at least one non-transitory computer readable medium of  claim 11 , wherein those blocks of the one or more memory blocks where the valid unit count is beneath a validity threshold and the hotness index count is beneath a hotness threshold are given a highest priority level for eviction from the plurality of priority levels, and wherein those blocks of the one or more memory blocks where the valid unit count is above the validity threshold and the hotness index count is above the hotness threshold are given a lowest priority level for eviction from the plurality of priority levels. 
     
     
         13 . The at least one non-transitory computer readable medium of  claim 9 , wherein the set of instructions, which when executed by the computing device, cause the computing device further to:
 select, via the memory controller, at least one memory block of the plurality of memory blocks for insertion based at least in part on the hotness data, wherein the insertion is from the x-level cell region to the single level cell region.