Gate isolation structures

Abstract

An IC structure and a method of forming the same are provided. In an embodiment, an exemplary method of forming the IC structure includes forming a first semiconductor fin and a second semiconductor fin protruding from a substrate, forming a high-k metal gate (HKMG) structure over the first semiconductor fin and the second semiconductor fin, forming a trench to separate the HKMG structure into two portions, conformally depositing a first dielectric layer in the trench, depositing a second dielectric layer over the first dielectric layer to fill the trench, wherein the second dielectric layer includes nitrogen, and the first dielectric layer is free of nitrogen, and planarizing the first dielectric layer and second dielectric layer to form a gate isolation structure in the trench.

What is claimed is: 
     
         1 . A method, comprising:
 forming a first semiconductor fin and a second semiconductor fin protruding from a substrate;   forming a high-k metal gate (HKMG) structure over the first semiconductor fin and the second semiconductor fin;   forming a trench to separate the HKMG structure into two portions;   conformally depositing a first dielectric layer in the trench;   depositing a second dielectric layer over the first dielectric layer to fill the trench, wherein the second dielectric layer includes nitrogen, and the first dielectric layer is free of nitrogen; and   planarizing the first dielectric layer and second dielectric layer to form a gate isolation structure in the trench, wherein the gate isolation structure comprises a bottom portion extended into the substrate, a middle portion disposed between the first semiconductor fin and the second semiconductor fin, and a top portion over the first semiconductor fin and the second semiconductor fin, wherein a width of the top portion is greater than a width of the middle portion.   
     
     
         2 . The method of  claim 1 , wherein a dielectric constant of the second dielectric layer is greater than a dielectric constant of the first dielectric layer. 
     
     
         3 . The method of  claim 1 , wherein the first dielectric layer comprises silicon oxide, and the second dielectric layer comprises silicon nitride. 
     
     
         4 . The method of  claim 1 , further comprising:
 before the forming of the HKMG structure, forming an isolation feature between the first semiconductor fin and the second semiconductor fin,   wherein the trench further extends into the isolation feature.   
     
     
         5 . The method of  claim 4 , wherein the substrate comprises a first doped region with a first doping polarity and a second doped region with a second doping polarity different from the first doping polarity, wherein the first semiconductor fin protrudes from the first doped region, and the second semiconductor fin protrudes from the second doped region. 
     
     
         6 . The method of  claim 5 , wherein the trench further extends into both the first doped region and the second doped region. 
     
     
         7 . The method of  claim 1 , wherein the gate isolation structure comprises an upper portion and a lower portion, wherein the upper portion is wider than the lower portion. 
     
     
         8 . The method of  claim 1 , wherein a bottom surface of the gate isolation structure is below a bottom surface of the HKMG structure. 
     
     
         9 . A method, comprising:
 providing a workpiece comprising a first fin, a second fin, a third fin, and a fourth fin protruding from a substrate, wherein the first fin and the second fin protrude from a first doped region of the substrate, the third fin protrudes from a second doped region of the substrate, and the fourth fin protrudes from a third doped region of the substrate, the first doped region and the third doped region comprise a first doping polarity, and the second doped region comprises a second doping polarity different from the first doping polarity;   forming a gate structure extending over the first, second, third, and fourth fins;   performing an etching process to form a first trench and a second trench extending vertically through the gate structure, the first trench being disposed between the first fin and the second fin, the second trench being disposed between the third fin and the fourth fin;   depositing a dielectric liner in the first and second trenches; and   forming a dielectric fill layer over the dielectric liner to substantially fill the first and second trenches, thereby forming a first gate isolation structure in the first trench and a second gate isolation structure in the second trench, wherein the dielectric fill layer includes nitrogen, and the dielectric liner is free of nitrogen.   
     
     
         10 . The method of  claim 9 , wherein the dielectric liner comprises silicon oxide, the dielectric fill layer comprises silicon nitride. 
     
     
         11 . The method of  claim 9 , wherein a bottom surface of the first gate isolation structure is below a bottom surface of the second gate isolation structure. 
     
     
         12 . The method of  claim 9 , wherein each of the first doped region and the third doped region comprises a p well, and the second doped region comprises an n well. 
     
     
         13 . The method of  claim 9 , wherein the workpiece further comprises:
 a first isolation feature disposed between the first fin and second fin, and   a second isolation feature disposed between the third fin and the fourth fin,   wherein a bottom surface of the second isolation feature is lower than a bottom surface of the first isolation feature.   
     
     
         14 . The method of  claim 13 , wherein the first gate isolation structure further extends through the first isolation feature and extends into the first doped region, and the second gate isolation structure further extends through the second isolation feature and extends into the second doped region and the third doped region. 
     
     
         15 . The method of  claim 13 , wherein the first gate isolation structure further comprises an air gap disposed in the dielectric fill layer, and a top surface of the air gap is below a top surface of the first isolation feature. 
     
     
         16 . A semiconductor structure, comprising:
 a first transistor comprising:
 a first fin protruding from a substrate, and 
 a first gate structure disposed over the first fin; 
   a second transistor comprising:
 a second fin protruding from the substrate and separated from the first fin by a first isolation feature, and 
 a second gate structure disposed over the second fin; 
   a first dielectric feature configured to provide isolation between the first and second gate structures, wherein the first dielectric feature includes a dielectric fill layer and a dielectric liner extending along sidewall and bottom surfaces of the dielectric fill layer, and the dielectric fill layer includes nitrogen;   a third transistor comprising a third gate structure; and   a second dielectric feature configured to provide isolation between the second and third gate structures, wherein a bottom surface of the second dielectric feature is lower than a bottom surface of the first dielectric feature.   
     
     
         17 . The semiconductor structure of  claim 16 , wherein the first transistor comprises an n-type transistor, and the second transistor comprises a p-type transistor. 
     
     
         18 . The semiconductor structure of  claim 17 ,
 wherein a composition of the second dielectric feature is the same as a composition of the first dielectric feature.   
     
     
         19 . The semiconductor structure of  claim 16 , wherein the third transistor further comprises a third fin, wherein the third fin is separated from the second fin by a second isolation feature, and wherein the first dielectric feature extends through the first isolation feature, the second dielectric feature extends through the second isolation feature. 
     
     
         20 . The semiconductor structure of  claim 19 , wherein a depth of the first isolation feature is greater than a depth of the second isolation feature.