Interconnect structures in integrated circuit chips

Abstract

An integrated circuit (IC) chip package and a method of fabricating the same are disclosed. The IC chip package includes a device layer on a first surface of a substrate, a first interconnect structure on the device layer, and a second interconnect structure on the second surface of the substrate. The first interconnect structure includes a fault detection line in a first metal line layer and configured to emit an electrical or an optical signal that is indicative of a presence or an absence of a defect in the device layer, a metal-free region on the fault detection line, and a metal line adjacent to the fault detection line in the first metal line layer. The fault detection line is electrically connected to the device layer.

What is claimed is: 
     
         1 . A structure, comprising:
 a substrate with first and second surfaces;   a device layer disposed on the first surface of the substrate;   a first interconnect structure disposed on the device layer, comprising:
 a fault detection line disposed in a first metal line layer and configured to emit an electrical or an optical signal that is indicative of a presence or an absence of a defect in the device layer, wherein the fault detection line is electrically connected to the device layer; 
 a metal-free region disposed on the fault detection line; and 
 a metal line disposed adjacent to the fault detection line in the first metal line layer; and 
   a second interconnect structure disposed on the second surface of the substrate.   
     
     
         2 . The structure of  claim 1 , wherein the fault detection line comprises a fault detection area aligned with the metal-free region. 
     
     
         3 . The structure of  claim 1 , wherein the first interconnect structure comprises a second metal line disposed in a second metal line layer over the first metal line layer, and
 wherein the fault detection line comprises a first surface area aligned with the metal-free region and a second surface area overlapping with the second metal line.   
     
     
         4 . The structure of  claim 1 , wherein the fault detection line comprises a fault detection area with a surface area of at least about 20 nm by about 20 nm. 
     
     
         5 . The structure of  claim 1 , wherein the fault detection line is spaced apart from the metal line by a distance of at least about 20 nm. 
     
     
         6 . The structure of  claim 1 , wherein the device layer comprises a transistor with a source/drain region and a contact structure disposed on the source/drain region, and
 wherein the fault detection line is electrically connected to the contact structure.   
     
     
         7 . The structure of  claim 1 , wherein the first interconnect structure further comprises a stack of metal line layers disposed between the fault detection line and the device layer, and
 wherein the fault detection line is electrically connected to the device layer through a plurality of metal lines disposed in the stack of metal line layers.   
     
     
         8 . The structure of  claim 1 , wherein the fault detection line comprises a metal. 
     
     
         9 . The structure of  claim 1 , further comprising a conductive through-via disposed in the substrate, and
 wherein the device layer is electrically connected to the second interconnect structure through the conductive through-via.   
     
     
         10 . The structure of  claim 1 , wherein a first distance between the fault detection line and a top surface of the first interconnect structure is smaller than a second distance between the fault detection line and a bottom surface of the first interconnect structure. 
     
     
         11 . A structure, comprising:
 a first substrate with first and second surfaces;   a device layer disposed on the first surface of the first substrate;   a first interconnect structure disposed on the device layer, comprising:
 a first fault detection line disposed in a first metal line layer and configured to emit an electrical or an optical signal that is indicative of a presence or an absence of a defect in a first region of the device layer; 
 a second fault detection line disposed in a second metal line layer and configured to emit an electrical or an optical signal that is indicative of a presence or an absence of a defect in a second region of the device layer, wherein the first and second fault detection lines are non-overlapping with each other; and 
 first and second metal-free regions disposed on the first and second fault detection lines, respectively; 
   a second substrate disposed on the first interconnect structure; and   a second interconnect structure disposed on the second surface of the first substrate.   
     
     
         12 . The structure of  claim 11 , wherein the first and second metal line layers are separated by a via layer comprising a metal via. 
     
     
         13 . The structure of  claim 11 , wherein each of the first and second fault detection lines comprises a fault detection area with a surface area of at least about 20 nm by about 20 nm. 
     
     
         14 . The structure of  claim 11 , wherein the first metal line layer is a topmost metal line layer of the first interconnect structure. 
     
     
         15 . The structure of  claim 11 , wherein the first metal line layer is one of three topmost metal line layers of the first interconnect structure. 
     
     
         16 . The structure of  claim 11 , wherein a first distance between the first fault detection line and a top surface of the first interconnect structure is smaller than a second distance between the first fault detection line and a bottom surface of the first interconnect structure. 
     
     
         17 . A structure, comprising:
 a substrate;   a device layer disposed on the substrate;   an interconnect structure, comprising:
 metal lines disposed on the device layer; 
 a fault detection line, disposed on the metal lines, configured to emit an electrical or an optical signal that is indicative of a presence or an absence of a defect in the device layer, wherein a first distance between the fault detection line and a top surface of the interconnect structure is smaller than a second distance between the fault detection line and a bottom surface of the interconnect structure; and 
 a metal-free region disposed on the fault detection line; and 
   a conductive through-via disposed in the substrate.   
     
     
         18 . The structure of  claim 17 , wherein the fault detection line comprises a metal layer with a surface area of at least about 20 nm by about 20 nm. 
     
     
         19 . The structure of  claim 17 , wherein the fault detection line comprises a metal layer spaced apart from adjacent metal layers by a distance of at least about 20 nm. 
     
     
         20 . The structure of  claim 17 , wherein the device layer comprises a gate-all-around transistor.