Apparatus and method for configuring cooperative warps in vector computing system

Abstract

The invention relates to an apparatus for configuring cooperative warps in a vector computing system. The apparatus includes general-purpose registers (GPRs); an arithmetic logical unit (ALU); and a warp instruction scheduler. The warp instruction scheduler is arranged operably to: allow each of a plurality of warps to access to data of a whole or a designated portion of the GPRs through the ALU in accordance with a configuration by a software when being executed; and complete calculations of each warp through the ALU.

What is claimed is: 
     
         1 . An apparatus for configuring cooperative warps in a vector computing system, comprising:
 a plurality of general-purpose registers (GPRs);   an arithmetic logical unit (ALU), coupled to the GPRs;   a warp instruction scheduler, coupled to the ALU, arranged operably to: allow each of a plurality of warps to access data of a whole or a designated portion of the GPRs through the ALU in accordance with a configuration while a software is executed; and complete calculations of each warp through the ALU; and   a plurality of resource-per-warp registers,   wherein each resource-per-warp register is associated with one warp, and is arranged operably to: store a base address corresponding to an associated warp,   wherein the warp instruction scheduler before sending an instruction associated with one warp to the ALU is arranged operably to: modify a source address and a destination address of the instruction in accordance with content of a corresponding resource-per-warp register, thereby enabling the instruction when being executed by the ALU to access the designated portion of the GPRs only,   wherein the content of the corresponding resource-per-warp register is set while the software is executed,   wherein the warps comprise a consumer warp and a producer warp, each of the consumer warp and the producer warp is composed of group of threads, and each thread is a basic unit that is run by hardware,   wherein executions of a plurality of instructions in the consumer warp refer to execution results of a plurality of instructions in the producer warp,   wherein the warp instruction scheduler is arranged operably to: acquire a first barrier instruction for the consumer warp from an instruction cache, force the consumer warp to a waiting state, obtain a producer instruction for the producer warp from the instruction cache, modify a first source address and a first destination address of the producer instruction in accordance with content of a corresponding resource-per-warp register, and send the producer instruction with a modified first source address and a modified first destination address to the ALU in response to an acquisition of the first barrier instruction for the consumer warp from the instruction cache,   wherein the warp instruction scheduler is arranged operably to: acquire a second barrier instruction for the producer warp from the instruction cache, wake up the consumer warp, obtain a consumer instruction for the consumer warp from the instruction cache, modify a second source address and a second destination address of the consumer instruction in accordance with content of a corresponding resource-per-warp register, and send the consumer instruction with a modified second source address and a modified second destination address to the ALU in response to an acquisition of the second barrier instruction for the producer warp from the instruction cache,   wherein the consumer warp and the producer warp are configured to associate with an overlapping block in the GPRs by setting the corresponding resource-per-warp registers,   wherein the overlapping block is for performing direct data exchange between the consumer warp and the producer warp.   
     
     
         2 . The apparatus of  claim 1 , wherein the apparatus does not allocate the whole or the designated portion of the GPRs for each warp, in advance. 
     
     
         3 . The apparatus of  claim 1 , comprising:
 wherein each resource-per-warp register is arranged operably to: map a data access for a corresponding warp to a designated portion of the GPRs.   
     
     
         4 . The apparatus of  claim 1 , wherein the consumer warp requires to refer to an execution result of an instruction in the producer warp. 
     
     
         5 . A method for configuring cooperative warps in a vector computing system, performed by a warp instruction scheduler, the method comprising:
 allowing each of a plurality of warps to access data of a whole or a designated portion of general-purpose registers (GPRs) through an arithmetic logical unit (ALU) in accordance with a configuration by a software when being executed; and   completing calculations of each warp through the ALU,   the method, performed by the warp instruction scheduler, comprising:   providing a base address corresponding to each warp; and   before sending an instruction associated with one warp to the ALU, modifying a source address and a destination address of the instruction in accordance with a corresponding base address, thereby enabling the instruction when being executed by the ALU to access the designated portion of the GPRs only,   wherein the corresponding base address is provided according to a content of a corresponding resource-per-warp register, which is set while a software is executed,   wherein the warps comprise a consumer warp and a producer warp, each of the consumer warp and the producer warp is composed of group of threads, and each thread is a basic unit that is run by hardware,   wherein executions of a plurality of instructions in the consumer warp refer to execution results of a plurality of instructions in the producer warp,   the method, performed by the warp instruction scheduler, comprising:   acquiring a first barrier instruction for the consumer warp from an instruction cache;   forcing the consumer warp to a waiting state, obtaining a producer instruction for the producer warp from the instruction cache, modifying a first source address and a first destination address of the producer instruction in accordance with a corresponding base address for the producer warp, and sending the producer instruction with a modified first source address and a modified first destination address to the ALU in response to an acquisition of the first barrier instruction for the consumer warp from the instruction cache;   acquiring a second barrier instruction for the producer warp from the instruction cache; and   waking up the consumer warp, modifying a second source address and a second destination address of a consumer instruction in accordance with a corresponding base address for the consumer warp, and sending the consumer instruction with a modified second source address and a modified second destination address to the ALU in response to an acquisition of the second barrier instruction for the producer warp from the instruction cache,   wherein the consumer warp and the producer warp are configured to associate with an overlapping block in the GPRs by setting the corresponding resource-per-warp registers,   wherein the overlapping block is for performing direct data exchange between the consumer warp and the producer warp.   
     
     
         6 . The method of  claim 5 , wherein the streaming multiprocessor comprises the GPRs and the ALU. 
     
     
         7 . The method of  claim 5 , wherein the streaming multiprocessor does not allocate the whole or the designated portion of the GPRs for each warp, in advance. 
     
     
         8 . The method of  claim 5 , wherein the consumer warp requires to refer to an execution result of an instruction in the producer warp. 
     
     
         9 . The method of  claim 5 , comprising:
 mapping a data access for each of the warps to a designated portion of GPRs in accordance with content of a plurality of resource-per-warp registers.   
     
     
         10 . The method of  claim 9 , wherein the streaming multiprocessor comprises the GPRs, the ALU, and the resource-per-warp registers.