Electronic communication system and method

Abstract

An addressably switchable interconnecting device, comprising an AXI stream switch having a plurality of input/output ports, configured so as to receive, into a first input/output port, data and control signals as well as a switch destination output port signal, to connect the first input/output port to a second input/output port depending on the switch destination output port signal, so as to pass the data and control signals from the first input/output port through the stream switch to the second input/output port, and further comprising a switch destination output port signal generating device for generating the switch destination output port signal from the data signal. Also a communication system and a communication protocol using the addressably switchable interconnecting device.

What is claimed is: 
     
         1 . An electronic communication system, comprising:
 an addressably switchable interconnecting device, comprising a stream switch having a plurality of input/output ports;   a switch destination output port signal generator configured to generate and output a switch destination output signal;   a first input/output port, of said plurality of input/output ports, configured so as to receive a data signal, a control signal, and the switch destination output port signal; and   a second input/output port, of said plurality of input/output ports, connected to said first input/output port by a connection that is formed in accordance with the switch destination output port signal;   wherein the addressably switchable interconnecting device further comprises:
 a data first-in/first-out buffer for receiving, buffering, and outputting the data signal and the control signal to the first input/output port; and 
   wherein the addressably switchable interconnecting device further comprises:
 a first single-beat buffer for receiving the data signal and the control signal from the data first-in/first-out buffer, buffering the data signal and the control signal, and outputting the data signal and the control signal to the first input/output port and to the switch destination output port signal generating device. 
   
     
     
         2 . The electronic communication system set forth in  claim 1 , wherein the addressably switchable interconnecting device further comprises:
 a second single-beat buffer for receiving the data signal and a control signal from the second input/output port, for buffering the data signal, and for outputting the data signal and the control signal.   
     
     
         3 . The electronic communication system set forth in  claim 1 , wherein:
 the addressably switchable interconnecting device is configured so as to operate using an Advanced Extensible Interface (“AXI”) streaming protocol, and wherein a control signal is an AXI streaming protocol control signal.   
     
     
         4 . The electronic communication system set forth in  claim 1 , wherein:
 the switch destination output port signal generating device comprises a lookup table.   
     
     
         5 . The electronic communication system set forth in  claim 4 , wherein:
 the switch destination output port signal generating device is configured so as to receive a routing header beat in the data signal and to apply the routing header beat to the lookup table to generate the switch destination output port signal.   
     
     
         6 . The electronic communication system set forth in  claim 5 , wherein:
 the switch destination output port signal generating device is configured so that, after a switch destination output port signal is generated, that switch destination output port signal is maintained throughout a subsequent data stream until the switch destination output port signal is cleared by a control signal.   
     
     
         7 . The electronic communication system set forth in  claim 6 , comprising:
 a plurality of said addressably switchable interconnecting devices;   a first protocol converting device, connected through an interconnection to a port of a first addressably switchable interconnecting device, of said plurality of addressably switchable interconnecting devices, for converting between the Advanced Extensible Interface (“AXI”) streaming protocol and a second streaming protocol;   
       a second protocol converting device, connected through an interconnection to a port of a second addressably switchable interconnecting device, of said plurality of addressably switchable interconnecting devices, for converting between the AXI streaming protocol and the second streaming protocol; 
       a first high-speed transceiver that is connected through an interconnection to the first protocol converting device; 
       a second high-speed transceiver that is connected through an interconnection to the second protocol converting device; and 
       a transceiver-transceiver interconnection connected between the first high-speed transceiver and the second high-speed transceiver. 
     
     
         8 . The electronic communication system, set forth in  claim 7 , wherein:
 the first addressably switchable interconnecting device, the first protocol converting device, the first high-speed transceiver, the second addressably switchable interconnecting device, the second protocol converting device, and the second high-speed transceiver are all arranged on a single circuit board.   
     
     
         9 . The electronic communication system, set forth in  claim 7 , wherein:
 the first addressably switchable interconnecting device, the first protocol converting device, and the first high-speed transceiver are all arranged on a first circuit board, and the second addressably switchable interconnecting device, the second protocol converting device, and the second high-speed transceiver are all arranged on a second circuit board.   
     
     
         10 . The electronic communication system set forth in  claim 9 , wherein:
 the first circuit board and the second circuit board are disposed in separate slots.   
     
     
         11 . The electronic communication system set forth in  claim 9 , wherein:
 the first circuit board and the second circuit board are disposed in separate boxes.   
     
     
         12 . The electronic communication system set forth in  claim 7 , wherein:
 the second streaming protocol is an AMD Aurora protocol.   
     
     
         13 . The electronic communication system set forth in  claim 7 , wherein:
 the transceiver-transceiver interconnection is a backplane, an optical connector, or a high-speed printed circuit board trace.   
     
     
         14 . An electronic communication method including the steps of:
 generating a routing header and prepending it to data in a stream in a source endpoint device that is connected to an endpoint of a field programmable grid array;   shifting the routing header through a first-in/first-out buffer under Advanced Extensible Interface (“AXI”) streaming control;   shifting the routing header through a single-beat buffer under AXI streaming control;   applying the routing header to a switch destination output port signal generating device to generate and latch a switch destination output port signal;   applying the switch destination output port signal to an AXI stream switch to establish a connection between a first input/output port of that switch and a second input/output port of that switch;   shifting the first beat of the AXI streaming packet into a second single-beat buffer, connected to the second input/output port, under AXI streaming control;   shifting the first beat of the AXI streaming packet into a destination end point;   streaming payload data through a circuit that has been established, under AXI streaming control;   identifying the last beat in the stream;   unlatching the switch destination output port signal;   shifting the last beat of the AXI stream to a destination endpoint;   comparing a number of words of data received to a stream length field in the routing header to evaluate whether or not the entire AXI stream has been received; and   sending back, to the source end point, a message indicating that there has been a communication failure when the entire AXI stream has not been received.   
     
     
         15 . The electronic communication method set forth in  claim 14 , further including the steps of:
 comparing a number of words of data received to a stream length field in the routing header to evaluate whether or not the entire AXI stream has been received; and   if the entire AXI stream has been received, using the same steps as in  claim 14  to send back, to the source end point, a message indicating that the communication has been successful.   
     
     
         16 . The electronic communication method set forth in  claim 14 , further including the steps of:
 shifting a beat of the AXI stream from a second single-beat buffer into a first protocol converter to convert to a beat of a stream of a second streaming protocol;   transmitting a beat of the stream of the second streaming protocol from a first high-speed transceiver through an interconnection to a second high-speed transceiver;   converting a beat of the stream of the second streaming protocol into an AXI stream in a second protocol converter; and   shifting a beat from the second protocol converter into a first-in/first-out buffer.   
     
     
         17 . The electronic communication method set forth in  claim 16 , wherein:
 the second streaming protocol is an AMD Aurora protocol.