Transmitter including selectively enabled clock source based on digital transmit data

Abstract

An apparatus, including: a clock source configured to generate a local oscillator (LO) clock signal; a radio frequency digital-to-analog converter (RF DAC) configured to generate a radio frequency (RF) signal based on a data signal and the LO clock signal; and an idle data detector configured to: detect a stream of idle data in the data signal; and disable providing the LO clock signal to at least a portion of the RF DAC in response to detecting the stream of idle data.

What is claimed: 
     
         1 . An apparatus, comprising:
 a clock source configured to generate a local oscillator (LO) clock signal;   a radio frequency digital-to-analog converter (RF DAC) configured to generate a radio frequency (RF) signal based on a data signal and the LO clock signal; and   an idle data detector configured to:
 detect a stream of idle data in the data signal, wherein the stream of idle data follows a stream of data in the data signal; and 
 provide a disable signal to the clock source to disable generating the LO clock signal in response to detecting the stream of idle data, wherein the idle data detector is configured to provide the disable signal at a time interval after an end of the stream of data. 
   
     
     
         2 . The apparatus of  claim 1 , wherein the data signal comprises a transmit physical layer data signal. 
     
     
         3 . The apparatus of  claim 1 , wherein the time interval is programmable. 
     
     
         4 . The apparatus of  claim 1 , wherein the time interval is set to one or more unit intervals (UIs) of the data signal. 
     
     
         5 . The apparatus of  claim 1 , wherein another stream of data in the data signal follows the stream of idle data, and wherein the idle data detector is configured to provide an enable signal to the clock source to generate the LO clock signal at a time interval prior to a beginning of the another stream of data. 
     
     
         6 . The apparatus of  claim 5 , wherein the time interval is programmable. 
     
     
         7 . The apparatus of  claim 5 , wherein the time interval is set to one or more unit intervals (UIs) of the data signal. 
     
     
         8 . The apparatus of  claim 1 , wherein the data signal comprises a transmit physical layer data signal, and further comprising an ultra-wideband (UWB) pulse generator configured to generate a transmit UWB signal based on the transmit physical layer data signal and an oversampling clock signal. 
     
     
         9 . The apparatus of  claim 8 , wherein the disable signal is further operative to disable providing the oversampling clock signal to the UWB pulse generator in response to detecting the stream of idle data. 
     
     
         10 . The apparatus of  claim 1 , wherein the data signal comprises a transmit ultra-wideband (UWB) signal. 
     
     
         11 . The apparatus of  claim 1 , wherein the data signal comprises a set of significant bit groups, wherein each of the significant bit groups includes one or more significant bits. 
     
     
         12 . The apparatus of  claim 11 , wherein the RF DAC comprises:
 a set of RF DACs configured to generate a set of RF signal portions based on the set of significant bit groups, respectively; and   a signal combiner configured to combine the set of RF signal portions to generate the RF signal.   
     
     
         13 . The apparatus of  claim 12 , wherein the idle data detector is configured to: detect the stream of idle data in a first subset of one or more of the set of significant bit groups, wherein the disable signal is operative to disable generation of the LO clock signal for a first subset of one or more of the set of RF DACs corresponding to the first subset of one or more of the set of significant bit groups. 
     
     
         14 . The apparatus of  claim 13 , wherein the idle data detector is configured to:
 detect another stream of data in a second subset of one or more of the set of significant bit groups, wherein the another stream of data is concurrent with the stream of idle data; and   enable providing of the LO clock signal to a second subset of one or more of the set of RF DACs corresponding to the second subset of one or more of the set of significant bit groups.   
     
     
         15 . A method, comprising:
 generating a local oscillator (LO) clock signal;   generating a radio frequency (RF) signal based on a data signal and the LO clock signal;   detecting a stream of idle data in the data signal; and   gating the LO clock signal to cease generating at least a portion of the RF signal in response to detecting the stream of idle data, wherein the stream of idle data follows a stream of data in the data signal, and wherein gating the LO clock signal begins at a time interval after an end of the stream of data.   
     
     
         16 . The method of  claim 15 , wherein another stream of data in the data signal follows the stream of idle data, and further comprising ungating the LO clock signal to generate the at least portion of the RF signal at a time interval before a beginning of the another stream of data. 
     
     
         17 . The method of  claim 15 , wherein:
 the data signal comprises a set of significant bit groups, wherein each of the significant bit groups includes one or more significant bits; and   generating the RF signal comprises:
 generating a set of RF signal portions based on the set of significant bit groups, respectively; and 
 combining the set of RF signal portions to generate the RF signal. 
   
     
     
         18 . The method of  claim 17 , wherein gating the LO clock signal to cease generating the at least the portion of the RF signal, comprises:
 detecting the stream of idle data in one or more of the set of significant bit groups; and   gating the LO clock signal to cease generating one or more of the set of RF signal portions based on the one or more of the set of significant bit groups in which the stream of idle detected has been detected.   
     
     
         19 . An apparatus, comprising:
 a modem configured to generate a physical layer (“phy”) data signal;   an ultra-wideband (UWB) pulse generator configured to generate a UWB signal based on the phy data signal and a first clock signal;   a radio frequency digital-to-analog converter (RF DAC) configured to generate a radio frequency (RF) signal based on the UWB signal and a second clock signal;   a gating circuit configured to gate the second clock signal from being applied to the RF DAC in response to a pattern in the phy data signal, wherein the gating circuit is further configured to gate the first clock signal from being applied to the UWB pulse generator in response to the pattern in the phy data signal; and   an idle data detector configured to detect the pattern in the phy data signal, wherein the pattern includes a stream of idle data, wherein:
 a stream of data in the phy data signal follows the stream of idle data; and 
 the gating circuit is configured to pass the second clock signal to the RF DAC at a time interval prior to a beginning of the stream of data. 
   
     
     
         20 . The apparatus of  claim 19 , wherein:
 the stream of idle data follows a stream of data in the phy data signal; and   the gating circuit is configured to gate the second clock signal from being applied to the RF DAC at another time interval after an end of the stream of data.   
     
     
         21 . An apparatus, comprising:
 a modem configured to generate a physical layer (“phy”) data signal;   an ultra-wideband (UWB) pulse generator configured to generate a UWB signal based on the phy data signal and a first clock signal, wherein the UWB signal comprises a set of significant bit groups;   a set of radio frequency digital-to-analog converters (RF DACs) configured to generate a set of radio frequency (RF) signals based on the set of significant bit groups of the UWB signal and a second clock signal, respectively;   an idle data detector configured to generate a set of control signals based on detecting a set of idle data stream in the set of significant bit groups, respectively; and   a gating circuit configured to pass or gate the second clock signal to or from the set of RF DACs based on the set of control signals, respectively, wherein the idle data detector is configured to modify the set of control signals based on a time interval prior to a beginning of a set of data stream following the set of idle data stream in the set of significant bit groups, respectively.   
     
     
         22 . The apparatus of  claim 21 , wherein the idle data detector is configured to modify the set of control signals based on a time interval after an end of a set of data stream preceding the set of idle data stream in the set of significant bit groups, respectively. 
     
     
         23 . The apparatus of  claim 21 , further comprising a signal combiner configured to combine the set of RF signals to generate an RF signal. 
     
     
         24 . The apparatus of  claim 23 , further comprising:
 an RF front end configured to process the RF signal to generate a transmit RF signal; and   at least one antenna configured to wirelessly radiate the transmit RF signal.