Power control circuit for memory circuit based on complementary field effect transistor devices

Abstract

An integrated circuit device includes a first transistor having a first-type channel and a second transistor having a second-type channel at a front side of a substrate. The first transistor is stacked over the second transistor. The integrated circuit device also includes a power line connected to a source terminal of the first transistor. The first transistor has a gate terminal configured to receive a control signal and has a drain terminal connected to both a gate terminal and a drain terminal of the second transistor. The integrated circuit device further includes a memory power line connected to a source terminal of the second transistor and a memory circuit configured to receive a supply voltage from the memory power line.

What is claimed is: 
     
         1 . An integrated circuit device comprising:
 a substrate;   a first transistor having a first-type channel and a second transistor having a second-type channel at a front side of the substrate, wherein the first transistor is stacked over the second transistor;   a power line connected to a source terminal of the first transistor, the first transistor having a gate terminal configured to receive a control signal and having a drain terminal connected to both a gate terminal and a drain terminal of the second transistor;   a memory power line connected to a source terminal of the second transistor;   a third transistor having either a first-type channel or a second-type channel connected between the drain terminal of the first transistor and the memory power line, wherein the third transistor has a gate terminal connected to a drain terminal thereof; and   a memory circuit configured to receive a supply voltage from the memory power line.   
     
     
         2 . The integrated circuit device of  claim 1 , wherein the third transistor has the first-type channel, and wherein the third transistor has a source terminal connected to the drain terminal of the first transistor. 
     
     
         3 . The integrated circuit device of  claim 1 , wherein the third transistor has the second-type channel, and wherein the third transistor has a source terminal connected to the memory power line. 
     
     
         4 . The integrated circuit device of  claim 1 , further comprising:
 a front-side conductor in a front-side metal layer above the first transistor and the second transistor; and   a back-side conductor in a back-side metal layer at a back side of the substrate.   
     
     
         5 . An integrated circuit device comprising:
 a substrate;   a first-type active-region structure extending in a first direction;   a first gate-conductor, extending in a second direction perpendicular to the first direction, intersecting the first-type active-region structure at a channel region of a first first-type transistor;   a first terminal conductor, extending in the second direction, intersecting the first-type active-region structure at a drain region of the first first-type transistor;   a second-type active-region structure extending in the first direction and stacked over the first-type active-region structure at a front side of the substrate, the second-type active-region structure being shifted from the first-type active-region structure along a third direction perpendicular to both the first direction and the second direction;   a second gate-conductor, extending in the second direction, intersecting the second-type active-region structure at a channel region of a first second-type transistor;   a second terminal conductor, extending in the second direction, intersecting the second-type active-region structure at a drain region of the first second-type transistor, wherein the second terminal conductor is conductively connected to the second gate-conductor, and wherein the second terminal conductor is conductively connected to the first terminal conductor intersecting the first-type active-region structure;   a memory power line connected to a source terminal of the first second-type transistor;   a third gate-conductor, extending in the second direction, intersecting the second-type active-region structure at a channel region of a second second-type transistor, and wherein the second second-type transistor has a source terminal conductively connected to the memory power line;   a third terminal conductor, extending in the second direction, intersecting the second-type active-region structure at a drain region of the second second-type transistor, wherein the third terminal conductor is conductively connected to the third gate-conductor, and wherein the third terminal conductor is conductively connected to the first terminal conductor intersecting the first-type active-region structure; and   a memory circuit configured to receive a supply voltage from the memory power line.   
     
     
         6 . The integrated circuit device of  claim 5 , further comprising:
 a front-side conductor in a front-side metal layer above the first-type active-region structure and the second-type active-region structure; and   a third terminal conductor, extending in the second direction, intersecting the first-type active-region structure at a source region of the first first-type transistor, wherein the third terminal conductor is conductively connected to the front-side conductor.   
     
     
         7 . The integrated circuit device of  claim 5 , further comprising:
 a back-side conductor in a back-side metal layer at a back side of the substrate; and   a third terminal conductor, extending in the second direction, intersecting the second-type active-region structure at a source region of the first second-type transistor, wherein the third terminal conductor is conductively connected to the back-side conductor.   
     
     
         8 . The integrated circuit device of  claim 5 , further comprising:
 a back-side conductor in a back-side metal layer at a back side of the substrate, and wherein the second terminal conductor is conductively connected to the second gate-conductor through the back-side conductor.   
     
     
         9 . The integrated circuit device of  claim 5 , wherein a source terminal of the first first-type transistor is configured to be maintained at an upper power supply voltage. 
     
     
         10 . The integrated circuit device of  claim 5 , wherein the first gate-conductor is configured to receive a power control signal. 
     
     
         11 . The integrated circuit device of  claim 5 , further comprising:
 a back-side conductor in a back-side metal layer at a back side of the substrate, and wherein the third terminal conductor is conductively connected to the third gate-conductor through the back-side conductor.   
     
     
         12 . The integrated circuit device of  claim 5 , wherein the first-type active-region structure is a PMOS active-region structure, and the second-type active-region structure is a NMOS active-region structure. 
     
     
         13 . The integrated circuit device of  claim 5 , wherein the first-type active-region structure is a NMOS active-region structure, and the second-type active-region structure is a PMOS active-region structure. 
     
     
         14 . An integrated circuit device comprising:
 a substrate;   a first-type active-region structure extending in a first direction;   a first gate-conductor, extending in a second direction perpendicular to the first direction, intersecting the first-type active-region structure at a channel region of a first first-type transistor;   a first terminal conductor, extending in the second direction, intersecting the first-type active-region structure at a drain region of the first first-type transistor;   a second-type active-region structure extending in the first direction and stacked over the first-type active-region structure at a front side of the substrate, the second-type active-region structure being shifted from the first-type active-region structure along a third direction perpendicular to both the first direction and the second direction;   a second gate-conductor, extending in the second direction, intersecting the second-type active-region structure at a channel region of a first second-type transistor;   a second terminal conductor, extending in the second direction, intersecting the second-type active-region structure at a drain region of the first second-type transistor, wherein the second terminal conductor is conductively connected to the second gate-conductor, and wherein the second terminal conductor is conductively connected to the first terminal conductor intersecting the first-type active-region structure;   a memory power line connected to a source terminal of the first second-type transistor;   a third gate-conductor, extending in the second direction, intersecting the first-type active-region structure at a channel region of a second first-type transistor, and wherein the second first-type transistor has a source terminal conductively connected to the first terminal conductor intersecting the first-type active-region structure;   a third terminal conductor, extending in the second direction, intersecting the first-type active-region structure at a drain region of the second first-type transistor, wherein the third terminal conductor is conductively connected to the third gate-conductor, and wherein the third terminal conductor is conductively connected to the memory power line; and   a memory circuit configured to receive a supply voltage from the memory power line.   
     
     
         15 . The integrated circuit device of  claim 14 , further comprising:
 a front-side conductor in a front-side metal layer above the first-type active-region structure and the second-type active-region structure, and wherein the third terminal conductor is conductively connected to the third gate-conductor through the front-side conductor.   
     
     
         16 . The integrated circuit device of  claim 14 , further comprising:
 a front-side conductor in a front-side metal layer above the first-type active-region structure and the second-type active-region structure; and   a fourth terminal conductor, extending in the second direction, intersecting the first-type active-region structure at a source region of the first first-type transistor, wherein the fourth terminal conductor is conductively connected to the front-side conductor.   
     
     
         17 . The integrated circuit device of  claim 14 , further comprising:
 a back-side conductor in a back-side metal layer at a back side of the substrate; and   a fourth terminal conductor, extending in the second direction, intersecting the second-type active-region structure at a source region of the first second-type transistor, wherein the fourth terminal conductor is conductively connected to the back-side conductor.   
     
     
         18 . The integrated circuit device of  claim 14 , further comprising:
 a back-side conductor in a back-side metal layer at a back side of the substrate, and wherein the second terminal conductor is conductively connected to the second gate-conductor through the back-side conductor.   
     
     
         19 . The integrated circuit device of  claim 14 , wherein a source terminal of the first first-type transistor is configured to be maintained at an upper power supply voltage. 
     
     
         20 . The integrated circuit device of  claim 14 , wherein the first gate-conductor is configured to receive a power control signal.