Three-dimensional semiconductor device and method of manufacturing the same

Abstract

A three-dimensional (3D) semiconductor device may include a stack structure and a vertical channel structure. The stack structure may include a first insulation pattern, a conductive pattern and a second insulation pattern. The conductive pattern may be arranged on the first insulation pattern. The second insulation pattern may be configured to physically contact an upper surface of the conductive pattern. The second insulation pattern may have a property different from a property of the first insulation pattern. The vertical channel structure may be formed through the stack structure.

What is claimed is: 
     
         1 . A three-dimensional (3D) semiconductor device comprising:
 a stack structure including a first insulation pattern, a conductive pattern arranged over the first insulation pattern, and a second insulation pattern configured to physically contact an upper surface of the conductive pattern, the second insulation pattern having a property different from a property of the first insulation pattern; and   at least one vertical channel structure arranged in the stack structure,   wherein the conductive pattern has a thickness thinner than a thickness of the first insulation pattern and thinner than a thickness of the second insulation pattern.   
     
     
         2 . The 3D semiconductor device of  claim 1 , wherein at least one of the first and second insulation patterns comprises an oxide material including silicon oxide and metal oxide, a nitride material including silicon nitride and silicon oxynitride, and an insulation material including impurities and an air gap. 
     
     
         3 . The 3D semiconductor device of  claim 1 , wherein the first and second insulation patterns include a same kind of an insulation material, and
 wherein a stoichiometry of the first insulation pattern is different from a stoichiometry of the second insulation pattern.   
     
     
         4 . The 3D semiconductor device of  claim 1 , wherein the first and second insulation patterns have a same thickness. 
     
     
         5 . The 3D semiconductor device of  claim 1  wherein the first and second insulation patterns comprise different kinds of insulation materials, and
 a dielectric constant range of the first insulation pattern overlaps a dielectric constant range of the second insulation pattern. 
 
     
     
         6 . The 3D semiconductor device of  claim 1 , wherein the conductive pattern comprises at least one conductive material layer. 
     
     
         7 . The 3D semiconductor device of  claim 6 , wherein the conductive material layer comprises molybdenum. 
     
     
         8 . The 3D semiconductor device of  claim 1 , wherein the conductive pattern comprises a barrier layer and a conductive layer, the barrier layer contacts a surface of the first insulation pattern, and the conductive layer contacts a surface of the second insulation pattern. 
     
     
         9 . A 3D semiconductor device comprising:
 a stack structure including a first insulating interlayer, a lower word line, a second insulating interlayer, and an upper word line sequentially stacked in a cell region and a contact region; and   at least one vertical channel structure including a data storage layer formed through the stack structure in the cell region,   wherein a property of the first insulating interlayer is different from a property of the second insulating interlayer, and   wherein a thickness of the second insulating interlayer in the contact region is thicker than a thickness of the second insulating interlayer in the cell region.   
     
     
         10 . The 3D semiconductor device of  claim 9 , wherein at least one of the first and second insulating interlayers includes an oxide material including silicon oxide and metal oxide, a nitride material including silicon nitride and silicon oxynitride, and an insulation material including impurities and an air gap. 
     
     
         11 . The 3D semiconductor device of  claim 10 , wherein the first and second insulating interlayers comprise a same kind of an insulation material, and
 wherein a stoichiometry of the first insulating interlayer is different from a stoichiometry of the second insulating interlayer.   
     
     
         12 . The 3D semiconductor device of  claim 9 , wherein the first and second insulating interlayers comprise different kinds of insulation materials, and
 a dielectric constant range of the first insulating interlayer overlaps a dielectric constant range of the second insulating interlayer.   
     
     
         13 . The 3D semiconductor device of  claim 9 , wherein at least one of a thickness of the upper word line and a thickness of the lower word line is thinner than a thickness of the first insulating interlayer and thinner than a thickness of the second insulating interlayer. 
     
     
         14 . The 3D semiconductor device of  claim 9 , wherein the upper and lower word lines include a molybdenum layer, and
 the molybdenum layer has a first surface configured to contact the first insulating interlayer and a second surface configured to contact the second insulating interlayer.   
     
     
         15 . The 3D semiconductor device of  claim 9 , wherein the upper and lower word lines include a barrier layer and a conductive layer formed on the barrier layer, and
 wherein the barrier layer contacts the first insulating interlayer and the conductive layer contacts the second insulating interlayer.   
     
     
         16 . The 3D semiconductor device of  claim 9 , wherein the lower word line is disposed along a lower surface of the second insulating interlayer, a side surface of the second insulating interlayer, and an end portion of an upper surface of the second insulating interlayer, and the upper word line is disposed on the upper surface of the second insulating interlayer, and
 wherein the upper word line and the lower word line are electrically separated from each other by a cut portion at the upper surface of the second insulating interlayer.   
     
     
         17 . The 3D semiconductor device of  claim 9 , further comprising:
 a first contact plug arranged in the contact region and contacting the upper word line; and   a second contact plug arranged in the contact region and contacting the lower word line,   wherein the first contact plug and the second contact plug have a same height.   
     
     
         18 . The 3D semiconductor device of  claim 9 , wherein the vertical channel structure further comprises at least one protruded portion arranged at an outer surface of the vertical channel structure corresponding to the second insulating interlayer. 
     
     
         19 . A 3D semiconductor device comprising:
 an insulating pattern comprising a lower surface, an upper surface and a side surface connecting the lower surface and the upper surface;   an upper word line disposed on the upper surface of the insulating pattern; and   a lower word line disposed along the lower surface, the side surface and an end portion of the upper surface of the insulating pattern,   wherein the upper word line is electrically separated from the lower word line.   
     
     
         20 . The 3D semiconductor device of  claim 19 , further comprising:
 a first contact plug disposed over the insulating pattern and configured to contact the upper word line; and   a second contact plug disposed over the insulating pattern and configured to contact the lower word line at the end portion.